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/external/llvm/test/MC/Disassembler/AMDGPU/
Dmubuf_vi.txt3 # VI: buffer_load_dword v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
4 0x00 0x00 0x50 0xe0 0x00 0x01 0x01 0x01
6 …uffer_load_dword v1, off, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
7 0x04 0x00 0x50 0xe0 0x00 0x01 0x01 0x01
9 …r_load_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x50,0xe0,0x00,0x01,0x01,0x01]
10 0x04 0x40 0x50 0xe0 0x00 0x01 0x01 0x01
12 …r_load_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x52,0xe0,0x00,0x01,0x01,0x01]
13 0x04 0x00 0x52 0xe0 0x00 0x01 0x01 0x01
15 …r_load_dword v1, off, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x50,0xe0,0x00,0x01,0x81,0x01]
16 0x04 0x00 0x50 0xe0 0x00 0x01 0x81 0x01
[all …]
Dsopc_vi.txt3 # GCN: s_cmp_eq_i32 s1, s2 ; encoding: [0x01,0x02,0x00,0xbf]
4 0x01 0x02 0x00 0xbf
6 # GCN: s_cmp_lg_i32 s1, s2 ; encoding: [0x01,0x02,0x01,0xbf]
7 0x01 0x02 0x01 0xbf
9 # GCN: s_cmp_gt_i32 s1, s2 ; encoding: [0x01,0x02,0x02,0xbf]
10 0x01 0x02 0x02 0xbf
12 # GCN: s_cmp_ge_i32 s1, s2 ; encoding: [0x01,0x02,0x03,0xbf]
13 0x01 0x02 0x03 0xbf
15 # GCN: s_cmp_lt_i32 s1, s2 ; encoding: [0x01,0x02,0x04,0xbf]
16 0x01 0x02 0x04 0xbf
[all …]
Dsmrd_vi.txt9 # VI: s_load_dword s1, s[2:3], 0x1 ; encoding: [0x41,0x00,0x02,0xc0,0x01,0x00,0x00,0x00]
10 0x41 0x00 0x02 0xc0 0x01 0x00 0x00 0x00
15 # VI: s_load_dwordx2 s[2:3], s[2:3], 0x1 ; encoding: [0x81,0x00,0x06,0xc0,0x01,0x00,0x00,0x00]
16 0x81 0x00 0x06 0xc0 0x01 0x00 0x00 0x00
21 # VI: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x01,0x0a,0xc0,0x01,0x00,0x00,0x00]
22 0x01 0x01 0x0a 0xc0 0x01 0x00 0x00 0x00
24 # VI: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x01,0x01,0x08,0xc0,0x04,0x00,0x00,0x00]
25 0x01 0x01 0x08 0xc0 0x04 0x00 0x00 0x00
27 # VI: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x02,0x0e,0xc0,0x01,0x00,0x00,0x00]
28 0x01 0x02 0x0e 0xc0 0x01 0x00 0x00 0x00
[all …]
Dflat_vi.txt3 # VI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
4 0x00 0x00 0x50 0xdc 0x03 0x00 0x00 0x01
6 # VI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
7 0x00 0x00 0x51 0xdc 0x03 0x00 0x00 0x01
9 # VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
10 0x00 0x00 0x53 0xdc 0x03 0x00 0x00 0x01
12 # VI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x80,0x01]
13 0x00 0x00 0x51 0xdc 0x03 0x00 0x80 0x01
15 # VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01]
16 0x00 0x00 0x53 0xdc 0x03 0x00 0x80 0x01
[all …]
Dvop3_vi.txt18 # VI: v_cmp_lt_f32_e64 s[2:3], |v4|, v6 ; encoding: [0x02,0x01,0x41,0xd0,0x04,0x0d,0x02,0x00]
19 0x02 0x01 0x41 0xd0 0x04 0x0d 0x02 0x00
27 # VI: v_cmp_lt_f32_e64 s[2:3], -|v4|, v6 ; encoding: [0x02,0x01,0x41,0xd0,0x04,0x0d,0x02,0x20]
28 0x02 0x01 0x41 0xd0 0x04 0x0d 0x02 0x20
30 # VI: v_cmp_lt_f32_e64 s[2:3], -|v4|, v6 ; encoding: [0x02,0x01,0x41,0xd0,0x04,0x0d,0x02,0x20]
31 0x02 0x01 0x41 0xd0 0x04 0x0d 0x02 0x20
75 # VI: v_mov_b32_e64 v1, v2 ; encoding: [0x01,0x00,0x41,0xd1,0x02,0x01,0x00,0x00]
76 0x01 0x00 0x41 0xd1 0x02 0x01 0x00 0x00
84 # VI: v_fract_f32_e64 v1, -v2 ; encoding: [0x01,0x00,0x5b,0xd1,0x02,0x01,0x00,0x20]
85 0x01 0x00 0x5b 0xd1 0x02 0x01 0x00 0x20
[all …]
Ddpp_vi.txt6 …p v0, v0 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x01,0xff]
7 0xfa 0x02 0x00 0x7e 0x00 0x01 0x01 0xff
9 … v0, v0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x1f,0x01,0xff]
10 0xfa 0x02 0x00 0x7e 0x00 0x1f 0x01 0xff
12 … v0, v0 row_ror:12 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x2c,0x01,0xff]
13 0xfa 0x02 0x00 0x7e 0x00 0x2c 0x01 0xff
15 … v0, v0 wave_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x30,0x01,0xff]
16 0xfa 0x02 0x00 0x7e 0x00 0x30 0x01 0xff
18 … v0, v0 wave_rol:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x34,0x01,0xff]
19 0xfa 0x02 0x00 0x7e 0x00 0x34 0x01 0xff
[all …]
Dvop2_vi.txt6 # VI: v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
7 0x01 0x00 0x89 0xd2 0x02 0x07 0x00 0x00
9 # VI: v_writelane_b32 v1, s2, s3 ; encoding: [0x01,0x00,0x8a,0xd2,0x02,0x06,0x00,0x00]
10 0x01 0x00 0x8a 0xd2 0x02 0x06 0x00 0x00
75 # VI: v_bfm_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x93,0xd2,0x02,0x07,0x02,0x00]
76 0x01 0x00 0x93 0xd2 0x02 0x07 0x02 0x00
87 # VI: v_bcnt_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8b,0xd2,0x02,0x07,0x02,0x00]
88 0x01 0x00 0x8b 0xd2 0x02 0x07 0x02 0x00
90 # VI: v_mbcnt_lo_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8c,0xd2,0x02,0x07,0x02,0x00]
91 0x01 0x00 0x8c 0xd2 0x02 0x07 0x02 0x00
[all …]
Dtrap_vi.txt13 # VI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
14 0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00
28 # VI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x86,0xff,0x01,0x00,0x00]
29 0x79,0xff,0x79,0x86,0xff,0x01,0x00,0x00
37 # VI: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x86,0x00,0x00,0x00,0x01]
38 0x71,0xff,0x78,0x86,0x00,0x00,0x00,0x01
58 # VI: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xfb,0xbe,0xac,0x4f,0x02,0x01]
59 0xff,0x00,0xfb,0xbe,0xac,0x4f,0x02,0x01
77 # VI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf4,0xbe]
78 0x7e,0x01,0xf4,0xbe
[all …]
/external/icu/icu4c/source/data/mappings/
Dlmb-excp.ucm21 <subchar> \x01\x3f
31 <U0027> \x01\x27 |0
32 <U005E> \x01\x23 |0
33 <U005E> \x01\x33 |3 # R5 compatibility
34 <U005E> \x01\x6D |3 # R5 compatibility
35 <U0060> \x01\x24 |0
36 <U0060> \x01\x34 |3 # R5 compatibility
37 <U007E> \x01\x21 |0
38 <U007E> \x01\x31 |3 # R5 compatibility
39 <U007E> \x01\x6C |3 # R5 compatibility
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dunpredictable-AI1cmp-arm.txt4 # CHECK: 0x01 0x10 0x50 0x03
5 0x01 0x10 0x50 0x03
8 # CHECK: 0x82 0x10 0x50 0x01
9 0x82 0x10 0x50 0x01
12 # CHECK: 0x02 0x10 0x50 0x01
13 0x02 0x10 0x50 0x01
16 # CHECK: 0x1f 0x01 0x52 0x01
17 0x1f 0x01 0x52 0x01
20 # CHECK: 0x10 0x11 0x52 0x01
21 0x10 0x11 0x52 0x01
[all …]
Dunpredictable-swp-arm.txt4 # CHECK: 0x9f 0x10 0x03 0x01
5 0x9f 0x10 0x03 0x01
8 # CHECK: 0x90 0xf0 0x03 0x01
9 0x90 0xf0 0x03 0x01
12 # CHECK: 0x90 0x1f 0x03 0x01
13 0x90 0x1f 0x03 0x01
16 # CHECK: 0x90 0x10 0x0f 0x01
17 0x90 0x10 0x0f 0x01
20 # CHECK: 0x90 0x10 0x01 0x01
21 0x90 0x10 0x01 0x01
[all …]
Dinvalid-thumbv8.txt8 [0x00 0xee 0x00 0x01]
11 # CHECK-NEXT: [0x00 0xee 0x00 0x01]
23 [0x00 0xfe 0x00 0x01]
26 # CHECK-NEXT: [0x00 0xfe 0x00 0x01]
38 [0x00 0xee 0x10 0x01]
41 # CHECK-NEXT: [0x00 0xee 0x10 0x01]
43 [0x00 0xfe 0x10 0x01]
46 # CHECK-NEXT: [0x00 0xfe 0x10 0x01]
58 [0x10 0xee 0x10 0x01]
61 # CHECK-NEXT: [0x10 0xee 0x10 0x01]
[all …]
Dinvalid-armv8.txt8 [0x00 0x01 0x00 0xee]
11 # CHECK-NEXT: [0x00 0x01 0x00 0xee]
23 [0x00 0x01 0x00 0xfe]
26 # CHECK-NEXT: [0x00 0x01 0x00 0xfe]
38 [0x10 0x01 0x00 0xee]
41 # CHECK-NEXT: [0x10 0x01 0x00 0xee]
43 [0x10 0x01 0x00 0xfe]
46 # CHECK-NEXT: [0x10 0x01 0x00 0xfe]
58 [0x10 0x01 0x10 0xee]
61 # CHECK-NEXT: [0x10 0x01 0x10 0xee]
[all …]
Dunpredictable-MRS-arm.txt4 # CHECK: 0x00 0xf0 0x0f 0x01
5 0x00 0xf0 0x0f 0x01
8 # CHECK: 0x00 0xf0 0x4f 0x01
9 0x00 0xf0 0x4f 0x01
12 # CHECK: 0x0f 0x0d 0x01 0x01
13 0x0f 0x0d 0x01 0x01
16 # CHECK: 0x0f 0x0d 0x40 0x01
17 0x0f 0x0d 0x40 0x01
Dunpredictable-ADDREXT3-arm.txt4 # CHECK: 0xd1 0xf1 0x5f 0x01
5 0xd1 0xf1 0x5f 0x01
7 # CHECK: 0xf1 0xf1 0x5f 0x01
8 0xf1 0xf1 0x5f 0x01
10 # CHECK: 0xf1 0xf1 0x5f 0x01
11 0xf1 0xf1 0x5f 0x01
13 # CHECK: 0xd1 0xe1 0x4f 0x01
14 0xd1 0xe1 0x4f 0x01
Dunpredictable-MUL-arm.txt4 # CHECK: 0x93 0x12 0x01 0x00
5 0x93 0x12 0x01 0x00
8 # CHECK: 0x92 0x0f 0x01 0x00
9 0x92 0x0f 0x01 0x00
12 # CHECK: 0x9f 0x02 0x01 0x00
13 0x9f 0x02 0x01 0x00
16 # CHECK: 0x92 0x01 0x0f 0x00
17 0x92 0x01 0x0f 0x00
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/MBlaze/
Dmblaze_fpu.txt8 0x58 0x01 0x10 0x00
11 0x58 0x01 0x10 0x80
14 0x58 0x01 0x11 0x00
17 0x58 0x01 0x11 0x80
20 0x58 0x01 0x03 0x80
23 0x58 0x01 0x03 0x00
26 0x58 0x01 0x02 0x80
29 0x58 0x01 0x12 0x00
32 0x58 0x01 0x12 0x10
35 0x58 0x01 0x12 0x20
[all …]
/external/icu/icu4c/source/test/testdata/
Dtest3.ucm31 <U00c0> \x05+\x01\x02\x0d |0
32 <U00c0> \x05+\x01\x02\x0e |3
43 <U101234>+<U50005>+<U60006> \x07+\x00+\x01\x02\x0f+\x09 |0
44 <U101234>+<U50005> \x07+\x00+\x01\x02\x0e+\x05 |0
45 <U101234>+<U60006> \x07+\x00+\x01\x02\x0f+\x06 |0
46 <U101234>+<U70007> \x07+\x00+\x01\x02\x0f |1
52 <U00c4><U00c4><U101234><U0005> \x05+\x01\x02\x0c |0
55 <U23456> \x01\x02\x0a |0
56 <U000b> \x01\x02\x0b |0
57 #unassigned \x01\x02\x0c
[all …]
Dtest2.ucm30 <U00c0> \x05+\x01\x0d |0
31 <U00c0> \x05+\x01\x0e |3
42 <U101234>+<U50005>+<U60006> \x07+\x00+\x01\x0f+\x09 |0
43 <U101234>+<U50005> \x07+\x00+\x01\x0e+\x05 |0
44 <U101234>+<U60006> \x07+\x00+\x01\x0f+\x06 |0
45 <U101234>+<U70007> \x07+\x00+\x01\x0f |1
51 <U00c4><U00c4><U101234><U0005> \x05+\x01\x0c |0
54 <U23456> \x01\x0a |0
55 <U000b> \x01\x0b |0
56 #unassigned \x01\x0c
[all …]
Dtest4.ucm48 <U23456> \x01\x02\x03\x0a |0
49 <U000b> \x01\x02\x03\x0b |0
50 #unassigned \x01\x02\x03\x0c
51 <U34567> \x01\x02\x03\x0d |3
52 <U000e> \x01\x02\x03\x0e |3
53 #unassigned \x01\x02\x03\x0f
61 <U30ab><U309a> \x01\x02\x03\x0a\x01\x02\x03\x0b\x01\x02\x03\x0c\x01\x02\x03\x0d\x01\x02\x03\x0e\x01…
/external/llvm/lib/Target/X86/
DX86InstrSVM.td19 def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB;
22 def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB;
25 def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB;
29 def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB;
33 def VMRUN32 : I<0x01, MRM_D8, (outs), (ins),
36 def VMRUN64 : I<0x01, MRM_D8, (outs), (ins),
41 def VMLOAD32 : I<0x01, MRM_DA, (outs), (ins),
44 def VMLOAD64 : I<0x01, MRM_DA, (outs), (ins),
49 def VMSAVE32 : I<0x01, MRM_DB, (outs), (ins),
52 def VMSAVE64 : I<0x01, MRM_DB, (outs), (ins),
[all …]
/external/boringssl/src/crypto/poly1305/
Dpoly1305_arm_asm.S64 # qhasm: reg128 x01
219 # qhasm: x01 aligned= mem128[input_0];input_0+=16
220 # asm 1: vld1.8 {>x01=reg128#9%bot->x01=reg128#9%top},[<input_0=int32#1,: 128]!
221 # asm 2: vld1.8 {>x01=d16->x01=d17},[<input_0=r0,: 128]!
462 # qhasm: r4[0,1] += x01[0] unsigned* z34[2]; r4[2,3] += x01[1] unsigned* z34[3]
463 # asm 1: vmlal.u32 <r4=reg128#16,<x01=reg128#9%bot,<z34=reg128#6%top
464 # asm 2: vmlal.u32 <r4=q15,<x01=d16,<z34=d11
477 # qhasm: r4[0,1] += x01[2] unsigned* z34[0]; r4[2,3] += x01[3] unsigned* z34[1]
478 # asm 1: vmlal.u32 <r4=reg128#16,<x01=reg128#9%top,<z34=reg128#6%bot
479 # asm 2: vmlal.u32 <r4=q15,<x01=d17,<z34=d10
[all …]
/external/llvm/test/MC/Disassembler/Mips/micromips-dsp/
Dvalid.txt19 0x01 0xe7 0xe8 0xbc # CHECK: extpv $15, $ac3, $7
21 0x01 0x98 0x1e 0x7c # CHECK: extr_r.w $12, $ac0, 24
25 0x01 0x43 0x1e 0xbc # CHECK: extrv_r.w $10, $ac0, $3
26 0x01 0xf4 0x6e 0xbc # CHECK: extrv_rs.w $15, $ac1, $20
27 0x01 0x10 0xbe 0xbc # CHECK: extrv_s.h $8, $ac2, $16
30 0x01 0x28 0x1a 0xbc # CHECK: maddu $ac0, $8, $9
31 0x01 0x6a 0xea 0xbc # CHECK: msub $ac3, $10, $11
32 0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13
42 0x01 0x2a 0x91 0x3c # CHECK: precequ.ph.qbr $9, $10
43 0x01 0x6c 0x93 0x3c # CHECK: precequ.ph.qbra $11, $12
[all …]
/external/llvm/test/MC/Disassembler/Mips/mips32/
Dvalid-mips32-el.txt14 0x4c 0x01 0x00 0x10 # CHECK: b 1332
15 0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
16 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
17 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
18 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
19 0x4c 0x01 0x26 0x11 # CHECK: beq $9, $6, 1332
20 0x4c 0x01 0xc1 0x04 # CHECK: bgez $6, 1332
21 0x4c 0x01 0xd1 0x04 # CHECK: bgezal $6, 1332
22 0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
23 0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
[all …]
/external/llvm/test/MC/ARM/
Dthumb2-narrow-dp.ll20 // CHECK: adds.w r1, r1, #8 @ encoding: [0x11,0xf1,0x08,0x01]
40 // CHECK: addseq.w r1, r1, #8 @ encoding: [0x11,0xf1,0x08,0x01]
62 // CHECK: addseq.w r0, r2, r1 @ encoding: [0x12,0xeb,0x01,0x00]
66 // CHECK: addseq.w r2, r2, r1 @ encoding: [0x12,0xeb,0x01,0x02]
120 // CHECK: ands.w r0, r2, r1 @ encoding: [0x12,0xea,0x01,0x00]
123 // CHECK: ands.w r0, r0, r1 @ encoding: [0x10,0xea,0x01,0x00]
125 // CHECK: and.w r0, r1, r0 @ encoding: [0x01,0xea,0x00,0x00]
129 // CHECK: ands.w r8, r8, r1 @ encoding: [0x18,0xea,0x01,0x08]
131 // CHECK: ands.w r1, r1, r8 @ encoding: [0x11,0xea,0x08,0x01]
164 // CHECK: andeq.w r0, r2, r1 @ encoding: [0x02,0xea,0x01,0x00]
[all …]

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