Searched refs:x55555555 (Results 1 – 9 of 9) sorted by relevance
/external/llvm/test/Transforms/InstCombine/ |
D | add2.ll | 90 ; y + (~((x >> 3) & 0x55555555) + 1) -> y - ((x >> 3) & 0x55555555) 105 ; y + (~(x & 0x55555555) + 1) -> y - (x & 0x55555555) 118 ; (y + 1) + ~(x & 0x55555555) -> y - (x & 0x55555555) 183 ; y + (~(x | 0x55555555) + 1) -> y - (x | 0x55555555) 195 ; (y + 1) + ~(x | 0x55555555) -> y - (x | 0x55555555)
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-popcnt.ll | 15 ; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0x55555555 33 ; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0x55555555
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/external/valgrind/none/tests/mips32/ |
D | mips32_dsp.stdout.exp-BE | 15 absq_s.ph $t2, $t4 :: rd 0x55555555 rt 0x55555555 DSPControl 0x0 60 absq_s.w $t2, $t4 :: rd 0x55555555 rt 0x55555555 DSPControl 0x0 109 addq.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 149 addq_s.ph $t2, $t4, $t8 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 194 addq_s.w $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 234 addsc $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 274 addu.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 314 addu_s.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 354 addwc $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 387 bitrev $t4, $t1 :: rd 0x0000aaaa rt 0x55555555 [all …]
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D | mips32_dsp.stdout.exp-LE | 15 absq_s.ph $t2, $t4 :: rd 0x55555555 rt 0x55555555 DSPControl 0x0 60 absq_s.w $t2, $t4 :: rd 0x55555555 rt 0x55555555 DSPControl 0x0 109 addq.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 149 addq_s.ph $t2, $t4, $t8 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 194 addq_s.w $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 234 addsc $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 274 addu.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 314 addu_s.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 354 addwc $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 387 bitrev $t4, $t1 :: rd 0x0000aaaa rt 0x55555555 [all …]
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/external/vulkan-validation-layers/libs/glm/detail/ |
D | intrinsic_integer.inl | 38 __m128i const Mask0 = _mm_set1_epi32(0x55555555); 92 __m128i const Mask0 = _mm_set1_epi32(0x55555555);
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/external/vulkan-validation-layers/libs/glm/gtx/ |
D | integer.inl | 49 x -= ((x >> 1) & 0x55555555);
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D | bit.inl | 393 REG1 = ((REG1 << 1) | REG1) & glm::uint32(0x55555555); 394 REG2 = ((REG2 << 1) | REG2) & glm::uint32(0x55555555);
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/external/valgrind/VEX/priv/ |
D | guest_arm64_toIR.c | 7529 IRTemp x55555555 = newTempV128(); in math_FOLDV() local 7537 assign(x55555555, mk_CatOddLanes16x8 (x54545454, x54545454)); in math_FOLDV() 7564 assign(xAllB, mk_CatOddLanes8x16 (x55555555, x55555555)); in math_FOLDV() 7565 assign(xAllA, mk_CatEvenLanes8x16(x55555555, x55555555)); in math_FOLDV() 7628 IRTemp x55555555 = newTempV128(); in math_FOLDV() local 7636 assign(x55555555, mk_CatOddLanes16x8 (x54545454, x54545454)); in math_FOLDV() 7647 assign(max54, binop(op, mkexpr(x55555555), mkexpr(x44444444))); in math_FOLDV()
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | basic-a64-instructions.txt | 2866 # CHECK: {{ands wzr,|tst}} wzr, #0x55555555
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