1 /*
2 * Copyright (c) 2010 The WebM project authors. All Rights Reserved.
3 *
4 * Use of this source code is governed by a BSD-style license
5 * that can be found in the LICENSE file in the root of the source
6 * tree. An additional intellectual property rights grant can be found
7 * in the file PATENTS. All contributing project authors may
8 * be found in the AUTHORS file in the root of the source tree.
9 */
10
11 #ifndef VPX_PORTS_X86_H_
12 #define VPX_PORTS_X86_H_
13 #include <stdlib.h>
14
15 #if defined(_MSC_VER)
16 #include <intrin.h> /* For __cpuidex, __rdtsc */
17 #endif
18
19 #include "vpx_config.h"
20 #include "vpx/vpx_integer.h"
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 typedef enum {
27 VPX_CPU_UNKNOWN = -1,
28 VPX_CPU_AMD,
29 VPX_CPU_AMD_OLD,
30 VPX_CPU_CENTAUR,
31 VPX_CPU_CYRIX,
32 VPX_CPU_INTEL,
33 VPX_CPU_NEXGEN,
34 VPX_CPU_NSC,
35 VPX_CPU_RISE,
36 VPX_CPU_SIS,
37 VPX_CPU_TRANSMETA,
38 VPX_CPU_TRANSMETA_OLD,
39 VPX_CPU_UMC,
40 VPX_CPU_VIA,
41
42 VPX_CPU_LAST
43 } vpx_cpu_t;
44
45 #if defined(__GNUC__) && __GNUC__ || defined(__ANDROID__)
46 #if ARCH_X86_64
47 #define cpuid(func, func2, ax, bx, cx, dx) \
48 __asm__ __volatile__("cpuid \n\t" \
49 : "=a"(ax), "=b"(bx), "=c"(cx), "=d"(dx) \
50 : "a"(func), "c"(func2));
51 #else
52 #define cpuid(func, func2, ax, bx, cx, dx) \
53 __asm__ __volatile__( \
54 "mov %%ebx, %%edi \n\t" \
55 "cpuid \n\t" \
56 "xchg %%edi, %%ebx \n\t" \
57 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
58 : "a"(func), "c"(func2));
59 #endif
60 #elif defined(__SUNPRO_C) || \
61 defined(__SUNPRO_CC) /* end __GNUC__ or __ANDROID__*/
62 #if ARCH_X86_64
63 #define cpuid(func, func2, ax, bx, cx, dx) \
64 asm volatile( \
65 "xchg %rsi, %rbx \n\t" \
66 "cpuid \n\t" \
67 "movl %ebx, %edi \n\t" \
68 "xchg %rsi, %rbx \n\t" \
69 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
70 : "a"(func), "c"(func2));
71 #else
72 #define cpuid(func, func2, ax, bx, cx, dx) \
73 asm volatile( \
74 "pushl %ebx \n\t" \
75 "cpuid \n\t" \
76 "movl %ebx, %edi \n\t" \
77 "popl %ebx \n\t" \
78 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
79 : "a"(func), "c"(func2));
80 #endif
81 #else /* end __SUNPRO__ */
82 #if ARCH_X86_64
83 #if defined(_MSC_VER) && _MSC_VER > 1500
84 #define cpuid(func, func2, a, b, c, d) \
85 do { \
86 int regs[4]; \
87 __cpuidex(regs, func, func2); \
88 a = regs[0]; \
89 b = regs[1]; \
90 c = regs[2]; \
91 d = regs[3]; \
92 } while (0)
93 #else
94 #define cpuid(func, func2, a, b, c, d) \
95 do { \
96 int regs[4]; \
97 __cpuid(regs, func); \
98 a = regs[0]; \
99 b = regs[1]; \
100 c = regs[2]; \
101 d = regs[3]; \
102 } while (0)
103 #endif
104 #else
105 #define cpuid(func, func2, a, b, c, d) \
106 __asm mov eax, func __asm mov ecx, func2 __asm cpuid __asm mov a, \
107 eax __asm mov b, ebx __asm mov c, ecx __asm mov d, edx
108 #endif
109 #endif /* end others */
110
111 // NaCl has no support for xgetbv or the raw opcode.
112 #if !defined(__native_client__) && (defined(__i386__) || defined(__x86_64__))
xgetbv(void)113 static INLINE uint64_t xgetbv(void) {
114 const uint32_t ecx = 0;
115 uint32_t eax, edx;
116 // Use the raw opcode for xgetbv for compatibility with older toolchains.
117 __asm__ volatile(".byte 0x0f, 0x01, 0xd0\n"
118 : "=a"(eax), "=d"(edx)
119 : "c"(ecx));
120 return ((uint64_t)edx << 32) | eax;
121 }
122 #elif (defined(_M_X64) || defined(_M_IX86)) && defined(_MSC_FULL_VER) && \
123 _MSC_FULL_VER >= 160040219 // >= VS2010 SP1
124 #include <immintrin.h>
125 #define xgetbv() _xgetbv(0)
126 #elif defined(_MSC_VER) && defined(_M_IX86)
xgetbv(void)127 static INLINE uint64_t xgetbv(void) {
128 uint32_t eax_, edx_;
129 __asm {
130 xor ecx, ecx // ecx = 0
131 // Use the raw opcode for xgetbv for compatibility with older toolchains.
132 __asm _emit 0x0f __asm _emit 0x01 __asm _emit 0xd0
133 mov eax_, eax
134 mov edx_, edx
135 }
136 return ((uint64_t)edx_ << 32) | eax_;
137 }
138 #else
139 #define xgetbv() 0U // no AVX for older x64 or unrecognized toolchains.
140 #endif
141
142 #if defined(_MSC_VER) && _MSC_VER >= 1700
143 #undef NOMINMAX
144 #define NOMINMAX
145 #ifndef WIN32_LEAN_AND_MEAN
146 #define WIN32_LEAN_AND_MEAN
147 #endif
148 #include <windows.h>
149 #if WINAPI_FAMILY_PARTITION(WINAPI_FAMILY_APP)
150 #define getenv(x) NULL
151 #endif
152 #endif
153
154 #define HAS_MMX 0x01
155 #define HAS_SSE 0x02
156 #define HAS_SSE2 0x04
157 #define HAS_SSE3 0x08
158 #define HAS_SSSE3 0x10
159 #define HAS_SSE4_1 0x20
160 #define HAS_AVX 0x40
161 #define HAS_AVX2 0x80
162 #ifndef BIT
163 #define BIT(n) (1 << n)
164 #endif
165
x86_simd_caps(void)166 static INLINE int x86_simd_caps(void) {
167 unsigned int flags = 0;
168 unsigned int mask = ~0;
169 unsigned int max_cpuid_val, reg_eax, reg_ebx, reg_ecx, reg_edx;
170 char *env;
171 (void)reg_ebx;
172
173 /* See if the CPU capabilities are being overridden by the environment */
174 env = getenv("VPX_SIMD_CAPS");
175
176 if (env && *env) return (int)strtol(env, NULL, 0);
177
178 env = getenv("VPX_SIMD_CAPS_MASK");
179
180 if (env && *env) mask = (unsigned int)strtoul(env, NULL, 0);
181
182 /* Ensure that the CPUID instruction supports extended features */
183 cpuid(0, 0, max_cpuid_val, reg_ebx, reg_ecx, reg_edx);
184
185 if (max_cpuid_val < 1) return 0;
186
187 /* Get the standard feature flags */
188 cpuid(1, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
189
190 if (reg_edx & BIT(23)) flags |= HAS_MMX;
191
192 if (reg_edx & BIT(25)) flags |= HAS_SSE; /* aka xmm */
193
194 if (reg_edx & BIT(26)) flags |= HAS_SSE2; /* aka wmt */
195
196 if (reg_ecx & BIT(0)) flags |= HAS_SSE3;
197
198 if (reg_ecx & BIT(9)) flags |= HAS_SSSE3;
199
200 if (reg_ecx & BIT(19)) flags |= HAS_SSE4_1;
201
202 // bits 27 (OSXSAVE) & 28 (256-bit AVX)
203 if ((reg_ecx & (BIT(27) | BIT(28))) == (BIT(27) | BIT(28))) {
204 if ((xgetbv() & 0x6) == 0x6) {
205 flags |= HAS_AVX;
206
207 if (max_cpuid_val >= 7) {
208 /* Get the leaf 7 feature flags. Needed to check for AVX2 support */
209 cpuid(7, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
210
211 if (reg_ebx & BIT(5)) flags |= HAS_AVX2;
212 }
213 }
214 }
215
216 return flags & mask;
217 }
218
219 // Note:
220 // 32-bit CPU cycle counter is light-weighted for most function performance
221 // measurement. For large function (CPU time > a couple of seconds), 64-bit
222 // counter should be used.
223 // 32-bit CPU cycle counter
x86_readtsc(void)224 static INLINE unsigned int x86_readtsc(void) {
225 #if defined(__GNUC__) && __GNUC__
226 unsigned int tsc;
227 __asm__ __volatile__("rdtsc\n\t" : "=a"(tsc) :);
228 return tsc;
229 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
230 unsigned int tsc;
231 asm volatile("rdtsc\n\t" : "=a"(tsc) :);
232 return tsc;
233 #else
234 #if ARCH_X86_64
235 return (unsigned int)__rdtsc();
236 #else
237 __asm rdtsc;
238 #endif
239 #endif
240 }
241 // 64-bit CPU cycle counter
x86_readtsc64(void)242 static INLINE uint64_t x86_readtsc64(void) {
243 #if defined(__GNUC__) && __GNUC__
244 uint32_t hi, lo;
245 __asm__ __volatile__("rdtsc" : "=a"(lo), "=d"(hi));
246 return ((uint64_t)hi << 32) | lo;
247 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
248 uint_t hi, lo;
249 asm volatile("rdtsc\n\t" : "=a"(lo), "=d"(hi));
250 return ((uint64_t)hi << 32) | lo;
251 #else
252 #if ARCH_X86_64
253 return (uint64_t)__rdtsc();
254 #else
255 __asm rdtsc;
256 #endif
257 #endif
258 }
259
260 #if defined(__GNUC__) && __GNUC__
261 #define x86_pause_hint() __asm__ __volatile__("pause \n\t")
262 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
263 #define x86_pause_hint() asm volatile("pause \n\t")
264 #else
265 #if ARCH_X86_64
266 #define x86_pause_hint() _mm_pause();
267 #else
268 #define x86_pause_hint() __asm pause
269 #endif
270 #endif
271
272 #if defined(__GNUC__) && __GNUC__
x87_set_control_word(unsigned short mode)273 static void x87_set_control_word(unsigned short mode) {
274 __asm__ __volatile__("fldcw %0" : : "m"(*&mode));
275 }
x87_get_control_word(void)276 static unsigned short x87_get_control_word(void) {
277 unsigned short mode;
278 __asm__ __volatile__("fstcw %0\n\t" : "=m"(*&mode) :);
279 return mode;
280 }
281 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
x87_set_control_word(unsigned short mode)282 static void x87_set_control_word(unsigned short mode) {
283 asm volatile("fldcw %0" : : "m"(*&mode));
284 }
x87_get_control_word(void)285 static unsigned short x87_get_control_word(void) {
286 unsigned short mode;
287 asm volatile("fstcw %0\n\t" : "=m"(*&mode) :);
288 return mode;
289 }
290 #elif ARCH_X86_64
291 /* No fldcw intrinsics on Windows x64, punt to external asm */
292 extern void vpx_winx64_fldcw(unsigned short mode);
293 extern unsigned short vpx_winx64_fstcw(void);
294 #define x87_set_control_word vpx_winx64_fldcw
295 #define x87_get_control_word vpx_winx64_fstcw
296 #else
x87_set_control_word(unsigned short mode)297 static void x87_set_control_word(unsigned short mode) {
298 __asm { fldcw mode }
299 }
x87_get_control_word(void)300 static unsigned short x87_get_control_word(void) {
301 unsigned short mode;
302 __asm { fstcw mode }
303 return mode;
304 }
305 #endif
306
x87_set_double_precision(void)307 static INLINE unsigned int x87_set_double_precision(void) {
308 unsigned int mode = x87_get_control_word();
309 x87_set_control_word((mode & ~0x300) | 0x200);
310 return mode;
311 }
312
313 extern void vpx_reset_mmx_state(void);
314
315 #ifdef __cplusplus
316 } // extern "C"
317 #endif
318
319 #endif // VPX_PORTS_X86_H_
320