| /external/llvm/docs/ |
| D | MIRLangRef.rst | 312 Registers section in Machine Instructions Format Reference
353 .. _machine-operands:
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| D | NVPTXUsage.rst | 196 '``llvm.nvvm.read.ptx.sreg.*``'
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenRegisters.h | 228 std::vector<CodeGenRegister*> Registers; variable
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| D | AsmWriterEmitter.cpp | 464 const std::vector<CodeGenRegister*> &Registers) { in emitRegisterNameString()
519 const std::vector<CodeGenRegister*> &Registers = in EmitGetRegisterName() local
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| D | RegisterInfoEmitter.cpp | 32 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters(); in runEnums() local
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| D | AsmMatcherEmitter.cpp | 176 std::set<Record*> Registers; member
915 const std::vector<CodeGenRegister*> &Registers = in BuildRegisterClasses() local
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| /external/mesa3d/src/mesa/swrast/ |
| D | s_atifragshader.c | 37 GLfloat Registers[6][4]; /** six temporary registers */ member
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| /external/llvm/utils/TableGen/ |
| D | AsmWriterEmitter.cpp | 494 const std::deque<CodeGenRegister> &Registers) { in emitRegisterNameString()
550 const auto &Registers = Target.getRegBank().getRegisters(); in EmitGetRegisterName() local
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| D | CodeGenRegisters.h | 491 std::deque<CodeGenRegister> Registers; variable
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| D | AsmMatcherEmitter.cpp | 198 RegisterSet Registers; member
1203 const auto &Registers = Target.getRegBank().getRegisters(); in buildRegisterClasses() local
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| D | RegisterInfoEmitter.cpp | 90 const auto &Registers = Bank.getRegisters(); in runEnums() local
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| D | CodeGenRegisters.cpp | 1325 const auto &Registers = RegBank.getRegisters(); in computeUberSets() local
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| /external/autotest/client/cros/ |
| D | power_utils.py | 522 class Registers(object): class
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| /external/syslinux/gpxe/src/drivers/net/ |
| D | 3c90x.h | 58 enum Registers { enum
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 1125 IValueT BaseReg, IValueT Registers) { in emitMultiMemOp()
2005 void AssemblerARM32::popList(const IValueT Registers, CondARM32::Cond Cond) { in popList()
2034 void AssemblerARM32::pushList(const IValueT Registers, CondARM32::Cond Cond) { in pushList()
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| D | IceTargetLoweringMIPS32.cpp | 2343 SmallBitVector Registers(RegMIPS32::Reg_NUM); in getRegisterSet() local
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| D | IceTargetLoweringARM32.cpp | 2185 SmallBitVector Registers(RegARM32::Reg_NUM); in getRegisterSet() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 274 SmallVector<unsigned, 8> Registers; member in __anon10a3738d0311::ARMOperand
2203 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers; in parseRegisterList() local
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 445 SmallVector<unsigned, 8> Registers; member in __anon58d02de10311::ARMOperand
3465 SmallVector<std::pair<unsigned, unsigned>, 16> Registers; in parseRegisterList() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 2875 static const MCPhysReg Registers[6][8] = { in fastLowerArguments() local
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