| /external/clang/test/CodeGenOpenCL/ |
| D | to_addr_builtin.cl | 17 //CHECK: %[[RET:.*]] = call i8 addrspace(1)* @to_global(i8 addrspace(4)* %[[ARG]])
18 //CHECK: %{{.*}} = bitcast i8 addrspace(1)* %[[RET]] to i32 addrspace(1)*
22 //CHECK: %[[RET:.*]] = call i8 addrspace(1)* @to_global(i8 addrspace(4)* %[[ARG]])
23 //CHECK: %{{.*}} = bitcast i8 addrspace(1)* %[[RET]] to i32 addrspace(1)*
27 //CHECK: %[[RET:.*]] = call i8 addrspace(1)* @to_global(i8 addrspace(4)* %[[ARG]])
28 //CHECK: %{{.*}} = bitcast i8 addrspace(1)* %[[RET]] to i32 addrspace(1)*
32 //CHECK: %[[RET:.*]] = call i8 addrspace(1)* @to_global(i8 addrspace(4)* %[[ARG]])
33 //CHECK: %{{.*}} = bitcast i8 addrspace(1)* %[[RET]] to i32 addrspace(1)*
37 //CHECK: %[[RET:.*]] = call i8 addrspace(3)* @to_local(i8 addrspace(4)* %[[ARG]])
38 //CHECK: %{{.*}} = bitcast i8 addrspace(3)* %[[RET]] to i32 addrspace(3)*
[all …]
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | global_atomics_i64.ll | 14 ; GCN: buffer_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 …
15 ; GCN: buffer_store_dwordx2 [[RET]]
36 ; CI: buffer_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-…
37 ; VI: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} g…
38 ; GCN: buffer_store_dwordx2 [[RET]]
57 ; GCN: buffer_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
58 ; GCN: buffer_store_dwordx2 [[RET]]
77 ; CI: buffer_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-…
78 ; VI: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} g…
79 ; GCN: buffer_store_dwordx2 [[RET]]
[all …]
|
| D | global_atomics.ll | 37 ; GCN: buffer_atomic_add [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}}
38 ; GCN: buffer_store_dword [[RET]]
59 ; SI: buffer_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr…
60 ; VI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
61 ; GCN: buffer_store_dword [[RET]]
80 ; GCN: buffer_atomic_add [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc
81 ; GCN: buffer_store_dword [[RET]]
100 ; SI: buffer_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr…
101 ; VI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
102 ; GCN: buffer_store_dword [[RET]]
[all …]
|
| D | flat_atomics_i64.ll | 14 ; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} …
15 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
35 ; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} …
36 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
55 ; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} …
56 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
74 ; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} …
75 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
94 ; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} …
95 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
[all …]
|
| D | flat_atomics.ll | 14 ; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}}
15 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
35 ; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
36 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
55 ; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
56 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
74 ; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
75 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
94 ; GCN: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
95 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
[all …]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | vec_cmp.ll | 56 ; CHECK: vcmpequb [[RET:[0-9]+]], 2, 3
57 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
66 ; CHECK: vcmpgtsb [[RET:[0-9]+]], 2, 3
67 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
76 ; CHECK: vcmpgtub [[RET:[0-9]+]], 2, 3
77 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
122 ; CHECK: vcmpgtsb [[RET:[0-9]+]], 3, 2
123 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
132 ; CHECK: vcmpgtub [[RET:[0-9]+]], 3, 2
133 ; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
[all …]
|
| /external/mesa3d/src/mesa/x86/ |
| D | common_x86_asm.S | 69 RET
94 RET
107 RET
121 RET
135 RET
149 RET
170 RET
213 RET
|
| /external/skia/platform_tools/ios/bin/ |
| D | ios_setup.sh | 95 RET="$( cat ${TARGET} )"
97 >&2 echo "Result: '${RET}'"
98 echo -e "${RET}"
166 local RET=1
169 RET=0
172 return $RET
|
| D | ios_path_exists | 23 RET=ios_path_exists $1
24 exit $RET
|
| /external/vulkan-validation-layers/libs/glm/gtx/ |
| D | bit.inl | 314 template <typename PARAM, typename RET>
315 GLM_FUNC_DECL RET bitfieldInterleave(PARAM x, PARAM y);
317 template <typename PARAM, typename RET>
318 GLM_FUNC_DECL RET bitfieldInterleave(PARAM x, PARAM y, PARAM z);
320 template <typename PARAM, typename RET>
321 GLM_FUNC_DECL RET bitfieldInterleave(PARAM x, PARAM y, PARAM z, PARAM w);
324 template <typename PARAM, typename RET>
325 inline RET bitfieldInterleave(PARAM x, PARAM y)
327 RET Result = 0;
333 template <typename PARAM, typename RET>
[all …]
|
| /external/llvm/test/Transforms/InstCombine/ |
| D | abs-1.ll | 18 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[ISPOS]], i32 %x, i32 [[NEG]]
20 ; CHECK-NEXT: ret i32 [[RET]]
28 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[ISPOS]], i64 %x, i64 [[NEG]]
30 ; CHECK-NEXT: ret i64 [[RET]]
38 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[ISPOS]], i64 %x, i64 [[NEG]]
40 ; CHECK-NEXT: ret i64 [[RET]]
|
| D | ffs-1.ll | 111 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[INC]], i32 0
113 ; CHECK-NEXT: ret i32 [[RET]]
122 ; CHECK-FFS-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[INC]], i32 0
124 ; CHECK-FFS-NEXT: ret i32 [[RET]]
134 ; CHECK-FFS-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[TRUNC]], i32 0
136 ; CHECK-FFS-NEXT: ret i32 [[RET]]
|
| /external/llvm/test/Transforms/LoopVectorize/ |
| D | iv_outside_user.ll | 7 ; CHECK: %[[RET:.*]] = phi i32 [ {{.*}}, %for.body ], [ %n.vec, %middle.block ]
8 ; CHECK: ret i32 %[[RET]]
30 ; CHECK: %[[RET:.*]] = phi i32 [ {{.*}}, %for.body ], [ %ind.escape, %middle.block ]
31 ; CHECK: ret i32 %[[RET]]
48 ; CHECK: %[[RET:.*]] = phi i32 [ {{.*}}, %for.body ], [ 2, %middle.block ]
49 ; CHECK: ret i32 %[[RET]]
68 ; CHECK: %[[RET:.*]] = phi i32* [ {{.*}}, %for.body ], [ %ind.escape, %middle.block ]
69 ; CHECK: ret i32* %[[RET]]
91 ; CHECK: %[[RET:.*]] = phi i32* [ %inc.lag1, %for.body ], [ %ind.escape, %middle.block ]
92 ; CHECK: ret i32* %[[RET]]
|
| /external/webrtc/webrtc/build/ |
| D | adb_shell.sh | 16 local RET ADB_LOG
20 RET=$(sed -e '$!d' "$ADB_LOG") # Last line contains status code.
22 return $RET
|
| /external/llvm/test/CodeGen/X86/ |
| D | implicit-null-checks.mir | 118 RET 0, %eax
122 RET 0, %eax
126 RET 0, %eax
171 RET 0, %eax
175 RET 0, %eax
212 RET 0, %eax
216 RET 0, %eax
220 RET 0, %eax
256 RET 0, %eax
260 RET 0, %eax
[all …]
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| /external/clang/test/CodeGenObjC/ |
| D | getter-property-type-mismatch.m | 32 // CHECK: define internal [[RET:%.*]]* @"\01-[BPXLAppDelegate arrayOfThings
33 // CHECK: [[THREE:%.*]] = bitcast [[OPQ:%.*]]* [[TWO:%.*]] to [[RET]]*
34 // CHECK: ret [[RET]]* [[THREE]]
|
| D | autorelease.m | 43 // CHECK: [[RET:%.*]] = alloca i32,
47 // CHECK: store i32 [[T2]], i32* [[RET]]
52 // CHECK-NEXT: store i32 0, i32* [[RET]]
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | tdc-06.ll | 15 ; CHECK: je [[RET:.L.*]]
22 ; CHECK: jo [[RET]]
29 ; CHECK: jl [[RET]]
44 ; CHECK: [[RET]]:
|
| /external/llvm/test/Transforms/InstSimplify/ |
| D | call-callconv.ll | 12 ; CHECK: %[[RET:.*]] = select i1 %[[ISPOS]], i32 %i, i32 %[[NEG]]
13 ; CHECK: ret i32 %[[RET]]
24 ; CHECK: %[[RET:.*]] = select i1 %[[ISPOS]], i32 %i, i32 %[[NEG]]
25 ; CHECK: ret i32 %[[RET]]
|
| D | floating-point-arithmetic.ll | 18 ; CHECK-NEXT: [[RET:%.*]] = fsub float -0.000000e+00, [[T1]]
19 ; CHECK-NEXT: ret float [[RET]]
30 ; CHECK-NEXT: [[RET:%.*]] = fsub float 0.000000e+00, [[T1]]
31 ; CHECK-NEXT: ret float [[RET]]
|
| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| D | nvc0_screen.c | 441 #define RET(x) do { \ in nvc0_screen_get_compute_param() macro
449 RET((uint64_t []) { 3 }); in nvc0_screen_get_compute_param()
452 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 })); in nvc0_screen_get_compute_param()
454 RET(((uint64_t []) { 65535, 65535, 65535 })); in nvc0_screen_get_compute_param()
457 RET(((uint64_t []) { 1024, 1024, 64 })); in nvc0_screen_get_compute_param()
459 RET((uint64_t []) { 1024 }); in nvc0_screen_get_compute_param()
462 RET((uint64_t []) { 1024 }); in nvc0_screen_get_compute_param()
464 RET((uint64_t []) { 512 }); in nvc0_screen_get_compute_param()
467 RET((uint64_t []) { 1ULL << 40 }); in nvc0_screen_get_compute_param()
471 RET((uint64_t []) { 96 << 10 }); in nvc0_screen_get_compute_param()
[all …]
|
| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| D | nv50_screen.c | 393 #define RET(x) do { \ in nv50_screen_get_compute_param() macro
401 RET((uint64_t []) { 2 }); in nv50_screen_get_compute_param()
403 RET(((uint64_t []) { 65535, 65535 })); in nv50_screen_get_compute_param()
405 RET(((uint64_t []) { 512, 512, 64 })); in nv50_screen_get_compute_param()
407 RET((uint64_t []) { 512 }); in nv50_screen_get_compute_param()
409 RET((uint64_t []) { 1ULL << 32 }); in nv50_screen_get_compute_param()
411 RET((uint64_t []) { 16 << 10 }); in nv50_screen_get_compute_param()
413 RET((uint64_t []) { 16 << 10 }); in nv50_screen_get_compute_param()
415 RET((uint64_t []) { 4096 }); in nv50_screen_get_compute_param()
417 RET((uint32_t []) { 32 }); in nv50_screen_get_compute_param()
[all …]
|
| /external/libvpx/libvpx/vpx_dsp/x86/ |
| D | subtract_sse2.asm | 67 RET
78 RET
89 RET
115 RET
127 RET
|
| D | vpx_convolve_copy_sse2.asm | 85 RET
109 RET
132 RET
157 RET
186 RET
216 RET
|
| /external/skia/src/gpu/gl/ |
| D | GrGLUtil.h | 206 #define GR_GL_CALL_RET(IFACE, RET, X) \ argument
208 GR_GL_CALL_RET_NOERRCHECK(IFACE, RET, X); \
213 #define GR_GL_CALL_RET_NOERRCHECK(IFACE, RET, X) \ argument
215 (RET) = (IFACE)->fFunctions.f##X; \
|