Searched refs:AddrIdx (Results 1 – 4 of 4) sorted by relevance
/external/llvm/lib/Target/Mips/MCTargetDesc/ |
D | MipsNaClELFStreamer.cpp | 116 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, in sandboxLoadStoreStackChange() argument 122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange() 149 unsigned AddrIdx; in EmitInstruction() local 151 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx, in EmitInstruction() 156 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx) in EmitInstruction() 162 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter); in EmitInstruction() 202 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, in isBasePlusOffsetMemoryAccess() argument 223 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess() 234 *AddrIdx = 1; in isBasePlusOffsetMemoryAccess() 242 *AddrIdx = 2; in isBasePlusOffsetMemoryAccess()
|
D | MipsMCNaCl.h | 20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
|
/external/llvm/lib/Target/AMDGPU/ |
D | SILoadStoreOptimizer.cpp | 171 int AddrIdx = AMDGPU::getNamedOperandIdx(I->getOpcode(), AMDGPU::OpName::addr); in findMatchingDSInst() local 172 const MachineOperand &AddrReg0 = I->getOperand(AddrIdx); in findMatchingDSInst() 173 const MachineOperand &AddrReg1 = MBBI->getOperand(AddrIdx); in findMatchingDSInst()
|
/external/llvm/lib/Target/Mips/ |
D | MipsDelaySlotFiller.cpp | 685 unsigned AddrIdx; in searchRange() local 686 if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) && in searchRange() 687 baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) || in searchRange()
|