Searched refs:Amt2 (Results 1 – 11 of 11) sorted by relevance
/external/llvm/test/CodeGen/X86/ |
D | rotate.ll | 7 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1] 8 %shift.upgrd.2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1] 17 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1] 18 %shift.upgrd.4 = zext i8 %Amt2 to i32 ; <i32> [#uses=1] 41 %Amt2 = sub i8 16, %Amt ; <i8> [#uses=1] 42 %shift.upgrd.6 = zext i8 %Amt2 to i16 ; <i16> [#uses=1] 51 %Amt2 = sub i8 16, %Amt ; <i8> [#uses=1] 52 %shift.upgrd.8 = zext i8 %Amt2 to i16 ; <i16> [#uses=1] 74 %Amt2 = sub i8 8, %Amt ; <i8> [#uses=1] 75 %C = lshr i8 %A, %Amt2 ; <i8> [#uses=1] [all …]
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/external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
D | rotate.ll | 7 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1] 8 %shift.upgrd.2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1] 17 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1] 18 %shift.upgrd.4 = zext i8 %Amt2 to i32 ; <i32> [#uses=1] 41 %Amt2 = sub i8 16, %Amt ; <i8> [#uses=1] 42 %shift.upgrd.6 = zext i8 %Amt2 to i16 ; <i16> [#uses=1] 51 %Amt2 = sub i8 16, %Amt ; <i8> [#uses=1] 52 %shift.upgrd.8 = zext i8 %Amt2 to i16 ; <i16> [#uses=1] 74 %Amt2 = sub i8 8, %Amt ; <i8> [#uses=1] 75 %C = lshr i8 %A, %Amt2 ; <i8> [#uses=1] [all …]
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/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/ |
D | rotl-2.ll | 8 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1] 9 %shift.upgrd.2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1] 18 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1] 19 %shift.upgrd.4 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
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D | rotl-64.ll | 15 %Amt2 = sub i8 64, %Amt 16 %Amt3 = zext i8 %Amt2 to i64
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/external/llvm/test/CodeGen/PowerPC/ |
D | rotl-2.ll | 9 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1] 10 %shift.upgrd.2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1] 19 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1] 20 %shift.upgrd.4 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
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D | rotl-64.ll | 15 %Amt2 = sub i8 64, %Amt 16 %Amt3 = zext i8 %Amt2 to i64
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/external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/ |
D | rotate_ops.ll | 67 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1] 68 %tmp2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1] 75 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1] 78 %tmp2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1] 135 %Amt2 = sub i8 8, %Amt ; <i8> [#uses=1] 136 %C = lshr i8 %A, %Amt2 ; <i8> [#uses=1] 143 %Amt2 = sub i8 8, %Amt ; <i8> [#uses=1] 144 %C = shl i8 %A, %Amt2 ; <i8> [#uses=1]
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
D | LegalizeIntegerTypes.cpp | 1399 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, in ExpandShiftWithKnownAmountBit() 1413 DAG.getNode(Op2, NVT, InL, Amt2)); in ExpandShiftWithKnownAmountBit()
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeIntegerTypes.cpp | 1565 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt, in ExpandShiftWithKnownAmountBit() local 1584 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2); in ExpandShiftWithKnownAmountBit()
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 20127 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) : Amt->getOperand(2); in LowerShift() local 20133 CanBeSimplified = Amt2 == Amt->getOperand(2) && in LowerShift() 20134 Amt2 == Amt->getOperand(3); in LowerShift() 20140 Amt2 = Amt->getOperand(2); in LowerShift() 20147 CanBeSimplified = Amt2 == Amt->getOperand(i); in LowerShift() 20152 Amt2 = Amt->getOperand(4); in LowerShift() 20156 CanBeSimplified = Amt2 == Amt->getOperand(j); in LowerShift() 20161 isa<ConstantSDNode>(Amt2)) { in LowerShift() 20168 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT); in LowerShift() 20187 SDValue Amt0, Amt1, Amt2, Amt3; in LowerShift() local [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86ISelLowering.cpp | 9896 SDValue Amt1, Amt2; in LowerShift() local 9908 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, in LowerShift() 9913 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), in LowerShift() 9919 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); in LowerShift()
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