| /external/vixl/test/aarch32/ |
| D | test-assembler-aarch32.cc | 559 __ Ands(r0, r1, r1); in TEST() local
571 __ Ands(r0, r0, Operand(r1, LSL, 4)); in TEST() local
583 __ Ands(r0, r0, Operand(r1, LSR, 4)); in TEST() local
595 __ Ands(r0, r0, Operand(r1, ASR, 4)); in TEST() local
607 __ Ands(r0, r0, Operand(r1, ROR, 1)); in TEST() local
621 __ Ands(r2, r0, Operand(r1, RRX)); in TEST() local
636 __ Ands(r2, r0, Operand(r1, RRX)); in TEST() local
647 __ Ands(r0, r0, 0xf); in TEST() local
658 __ Ands(r0, r0, 0x80000000); in TEST() local
3187 __ Ands(r0, r0, 0); in TEST() local
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| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 123 M(Ands) \
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| D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 123 M(Ands) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 123 M(Ands) \
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| D | test-simulator-cond-rd-rn-operand-const-a32.cc | 123 M(Ands) \
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| D | test-simulator-cond-rd-rn-operand-const-t32.cc | 123 M(Ands) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 123 M(Ands) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 123 M(Ands) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 123 M(Ands) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 123 M(Ands) \
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| D | test-disasm-a32.cc | 1591 COMPARE_T32(Ands(r3, r2, Operand(r2, LSR, r2)), in TEST()
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 698 void MacroAssembler::Ands(const Register& rd, in Ands() function in vixl::aarch64::MacroAssembler
708 Ands(AppropriateZeroRegFor(rn), rn, operand); in Tst()
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| D | macro-assembler-aarch64.h | 615 void Ands(const Register& rd, const Register& rn, const Operand& operand);
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 958 __ Ands(i.OutputRegister(), i.InputOrZeroRegister64(0), in AssembleArchInstruction() local
973 __ Ands(i.OutputRegister32(), i.InputOrZeroRegister32(0), in AssembleArchInstruction() local
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| /external/v8/src/arm64/ |
| D | macro-assembler-arm64-inl.h | 55 void MacroAssembler::Ands(const Register& rd, in Ands() function
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| D | macro-assembler-arm64.h | 177 inline void Ands(const Register& rd,
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| D | code-stubs-arm64.cc | 1467 __ Ands(string_encoding, string_type, kStringEncodingMask); in Generate()
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 1283 Ands(cond, rd, rn, operand); in And()
1294 Ands(cond, rd, rn, operand); in And()
1308 void Ands(Condition cond, Register rd, Register rn, const Operand& operand) { in Ands() function
1318 void Ands(Register rd, Register rn, const Operand& operand) { in Ands() function
1319 Ands(al, rd, rn, operand); in Ands()
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 826 __ Ands(w0, w1, Operand(w1)); in TEST() local
837 __ Ands(w0, w0, Operand(w1, LSR, 4)); in TEST() local
848 __ Ands(x0, x0, Operand(x1, ROR, 1)); in TEST() local
858 __ Ands(w0, w0, Operand(0xf)); in TEST() local
868 __ Ands(w0, w0, Operand(0x80000000)); in TEST() local
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