Searched refs:BaseOp (Results 1 – 9 of 9) sorted by relevance
/external/llvm/lib/Target/AMDGPU/ |
D | EvergreenInstructions.td | 492 field string BaseOp; 501 let BaseOp = name; 507 let BaseOp = name; 523 field string BaseOp; 531 let BaseOp = name; 537 let BaseOp = name;
|
D | R600Instructions.td | 1729 let RowFields = ["BaseOp"];
|
/external/llvm/lib/Target/ARM/ |
D | ARMLoadStoreOptimizer.cpp | 1443 const MachineOperand &BaseOp = MI.getOperand(2); in MergeBaseUpdateLSDouble() local 1444 unsigned Base = BaseOp.getReg(); in MergeBaseUpdateLSDouble() 1473 .addReg(BaseOp.getReg(), RegState::Define); in MergeBaseUpdateLSDouble() 1476 MIB.addReg(BaseOp.getReg(), RegState::Define) in MergeBaseUpdateLSDouble() 1479 MIB.addReg(BaseOp.getReg(), RegState::Kill) in MergeBaseUpdateLSDouble() 1579 const MachineOperand &BaseOp = MI->getOperand(2); in FixInvalidRegPairOp() local 1580 unsigned BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp() 1605 bool BaseKill = BaseOp.isKill(); in FixInvalidRegPairOp() 1606 bool BaseUndef = BaseOp.isUndef(); in FixInvalidRegPairOp()
|
/external/llvm/lib/Target/Hexagon/ |
D | HexagonInstrInfoV4.td | 688 class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC, 697 let BaseOpcode = BaseOp#"_AbsSet"; 727 class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp, 736 let BaseOpcode = BaseOp#"_AbsSet"; 1487 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp, 1489 let BaseOpcode = "POST_"#BaseOp in { 1608 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp, 1610 let BaseOpcode = BaseOp#_NVJ in { 1671 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> { 1672 let BaseOpcode = BaseOp#_NVJri in { [all …]
|
D | HexagonInstrInfo.td | 1493 multiclass JMP_base<string BaseOp, string ExtStr> { 1494 let BaseOpcode = BaseOp in { 1546 multiclass JMPR_base<string BaseOp> { 1547 let BaseOpcode = BaseOp in { 1592 multiclass JMPpt_base<string BaseOp> { 1593 let BaseOpcode = BaseOp in { 1600 multiclass JMPRpt_base<string BaseOp> { 1601 let BaseOpcode = BaseOp in { 1904 multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC, 1906 let BaseOpcode = "POST_"#BaseOp in { [all …]
|
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMLoadStoreOptimizer.cpp | 1090 const MachineOperand &BaseOp = MI->getOperand(2); in FixInvalidRegPairOp() local 1091 unsigned BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp() 1092 bool BaseKill = BaseOp.isKill(); in FixInvalidRegPairOp() 1093 bool BaseUndef = BaseOp.isUndef(); in FixInvalidRegPairOp()
|
/external/llvm/include/llvm/Target/ |
D | Target.td | 1261 // let RowFields = BaseOp 1262 // All add instruction predicated/non-predicated will have to set their BaseOp 1265 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' } 1266 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' } 1267 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
|
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86ISelLowering.cpp | 10050 unsigned BaseOp = 0; in LowerXALUO() local 10060 BaseOp = X86ISD::INC; in LowerXALUO() 10064 BaseOp = X86ISD::ADD; in LowerXALUO() 10068 BaseOp = X86ISD::ADD; in LowerXALUO() 10076 BaseOp = X86ISD::DEC; in LowerXALUO() 10080 BaseOp = X86ISD::SUB; in LowerXALUO() 10084 BaseOp = X86ISD::SUB; in LowerXALUO() 10088 BaseOp = X86ISD::SMUL; in LowerXALUO() 10107 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in LowerXALUO()
|
/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 19889 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio); in LowerScalarImmediateShift() local 19891 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp)); in LowerScalarImmediateShift() 20481 unsigned BaseOp = 0; in LowerXALUO() local 20490 BaseOp = X86ISD::INC; in LowerXALUO() 20494 BaseOp = X86ISD::ADD; in LowerXALUO() 20498 BaseOp = X86ISD::ADD; in LowerXALUO() 20505 BaseOp = X86ISD::DEC; in LowerXALUO() 20509 BaseOp = X86ISD::SUB; in LowerXALUO() 20513 BaseOp = X86ISD::SUB; in LowerXALUO() 20517 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL; in LowerXALUO() [all …]
|