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Searched refs:BaseOpcode (Results 1 – 23 of 23) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp881 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in EncodeInstruction() local
884 BaseOpcode = 0x0F; // Weird 3DNow! encoding. in EncodeInstruction()
895 EmitByte(BaseOpcode, CurByte, OS); in EncodeInstruction()
898 EmitByte(BaseOpcode, CurByte, OS); in EncodeInstruction()
905 EmitByte(BaseOpcode, CurByte, OS); in EncodeInstruction()
913 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); in EncodeInstruction()
917 EmitByte(BaseOpcode, CurByte, OS); in EncodeInstruction()
924 EmitByte(BaseOpcode, CurByte, OS); in EncodeInstruction()
937 EmitByte(BaseOpcode, CurByte, OS); in EncodeInstruction()
956 EmitByte(BaseOpcode, CurByte, OS); in EncodeInstruction()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagon.td82 // Instructions with the same BaseOpcode and isNVStore values form a row.
83 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isNT"];
98 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
110 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
122 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
134 let RowFields = ["BaseOpcode", "PredSense", "isNVStore"];
146 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
158 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
224 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
232 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
[all …]
DHexagonInstrInfoV60.td125 let BaseOpcode = baseOp;
164 let BaseOpcode = baseOp;
197 let BaseOpcode = baseOp;
298 let BaseOpcode = baseOp;
409 let BaseOpcode = baseOp;
452 let BaseOpcode = baseOp;
488 let BaseOpcode = baseOp;
592 let BaseOpcode = baseOp;
671 let isNVStorable = 1, BaseOpcode = "vS32b_ppu" in {
674 let isNonTemporal = 1, BaseOpcode = "vS32b_ppu" in
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DHexagonInstrInfoV3.td30 let BaseOpcode = "call";
47 let BaseOpcode = "call";
DHexagonInstrInfoV4.td134 let BaseOpcode = "andn_rr", CextOpcode = "andn" in
136 let BaseOpcode = "orn_rr", CextOpcode = "orn" in
600 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
697 let BaseOpcode = BaseOp#"_AbsSet";
736 let BaseOpcode = BaseOp#"_AbsSet";
771 let BaseOpcode = CextOp#"_shl";
833 let BaseOpcode = CextOp#"_shl";
985 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
1005 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
1144 let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
[all …]
DHexagonInstrInfo.td125 let BaseOpcode = mnemonic#_rr;
151 let BaseOpcode = mnemonic#_rr;
405 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
551 let CextOpcode = CextOp, BaseOpcode = CextOp in {
585 let BaseOpcode = BaseName in {
598 isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR",
627 CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0,
791 let BaseOpcode = mnemonic in {
832 let BaseOpcode = mnemonic in {
1494 let BaseOpcode = BaseOp in {
[all …]
DHexagonInstrFormats.td185 string BaseOpcode = "";
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86CodeEmitter.cpp725 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(Desc->TSFlags); in emitInstruction() local
760 MCE.emitByte(BaseOpcode); in emitInstruction()
772 MCE.emitByte(BaseOpcode); in emitInstruction()
820 MCE.emitByte(BaseOpcode + in emitInstruction()
854 MCE.emitByte(BaseOpcode); in emitInstruction()
864 MCE.emitByte(BaseOpcode); in emitInstruction()
876 MCE.emitByte(BaseOpcode); in emitInstruction()
891 MCE.emitByte(BaseOpcode); in emitInstruction()
905 MCE.emitByte(BaseOpcode); in emitInstruction()
944 MCE.emitByte(BaseOpcode); in emitInstruction()
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/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp1191 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in encodeInstruction() local
1194 BaseOpcode = 0x0F; // Weird 3DNow! encoding. in encodeInstruction()
1216 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1229 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1239 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1243 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1248 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1255 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1263 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1272 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); in encodeInstruction()
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/external/llvm/lib/Target/Mips/
DMicroMips64r6InstrInfo.td105 string BaseOpcode = instr_asm;
139 string BaseOpcode = "dclo";
149 string BaseOpcode = "dclz";
183 string BaseOpcode = instr_asm;
218 string BaseOpcode = instr_asm;
235 string BaseOpcode = instr_asm;
247 string BaseOpcode = instr_asm;
278 string BaseOpcode = instr_asm;
295 string BaseOpcode = "lld";
307 string BaseOpcode = "sd";
DMipsDSPInstrInfo.td267 string BaseOpcode = instr_asm;
278 string BaseOpcode = instr_asm;
289 string BaseOpcode = instr_asm;
300 string BaseOpcode = instr_asm;
312 string BaseOpcode = instr_asm;
323 string BaseOpcode = instr_asm;
334 string BaseOpcode = instr_asm;
344 string BaseOpcode = instr_asm;
356 string BaseOpcode = instr_asm;
367 string BaseOpcode = instr_asm;
[all …]
DMipsDSPInstrFormats.td14 // Instructions with the same BaseOpcode and isNVStore values form a row.
15 let RowFields = ["BaseOpcode"];
50 string BaseOpcode = opstr;
DMicroMips32r6InstrInfo.td569 string BaseOpcode = "lwp";
582 string BaseOpcode = "swp";
618 string BaseOpcode = opstr;
662 string BaseOpcode = instr_asm;
675 string BaseOpcode = opstr;
687 string BaseOpcode = opstr;
698 string BaseOpcode = opstr;
710 string BaseOpcode = opstr;
731 string BaseOpcode = opstr;
743 string BaseOpcode = opstr;
[all …]
DMipsInstrFormats.td43 // Instructions with the same BaseOpcode and isNVStore values form a row.
44 let RowFields = ["BaseOpcode"];
57 // Instructions with the same BaseOpcode and isNVStore values form a row.
58 let RowFields = ["BaseOpcode"];
117 string BaseOpcode = opstr;
DMips32r6InstrFormats.td18 // Instructions with the same BaseOpcode and isNVStore values form a row.
19 let RowFields = ["BaseOpcode"];
30 string BaseOpcode = opstr;
DMicroMipsDSPInstrFormats.td14 string BaseOpcode = opstr;
DMicroMipsInstrFPU.td147 let BaseOpcode = "LDC132";
DMipsInstrFPU.td413 let BaseOpcode = "LDC164";
422 let BaseOpcode = "LDC132";
DMicroMips32r6InstrFormats.td16 string BaseOpcode = opstr;
DMicroMipsDSPInstrInfo.td357 string BaseOpcode = "raddu.w.qb";
/external/llvm/docs/
DHowToUseInstrMappings.rst84 // instructions need to have same value for BaseOpcode field. It can be any
87 let RowFields = ["BaseOpcode"];
146 let BaseOpcode = "ADD";
154 let BaseOpcode = "ADD";
162 let BaseOpcode = "ADD";
169 ``PredRel`` is excluded from the analysis. ``BaseOpcode`` is another important
DWritingAnLLVMBackend.rst1850 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DGPRArith.cpp1317 #define TestImpl(Inst, Dst, BaseOpcode) \ in TEST_F() argument
1323 BaseOpcode | GPRRegister::Encoded_Reg_##Dst); \ in TEST_F()