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Searched refs:CMP0 (Results 1 – 8 of 8) sorted by relevance

/external/llvm/test/Transforms/InstCombine/
Ddemorgan-zext.ll76 ; CHECK-NEXT: [[CMP0:%.*]] = icmp ne i32 %x, 0
78 ; CHECK-NEXT: [[AND:%.*]] = and i1 [[CMP0]], [[CMP1]]
/external/llvm/test/Transforms/InstSimplify/
DAndOrXor.ll314 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i8 %i, 0
315 ; CHECK-NEXT: [[CONV0:%.*]] = zext i1 [[CMP0]] to i16
331 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq <2 x i8> %i, zeroinitializer
332 ; CHECK-NEXT: [[CONV0:%.*]] = zext <2 x i1> [[CMP0]] to <2 x i3>
/external/llvm/test/CodeGen/AMDGPU/
Dfdiv.f64.ll19 ; SI-DAG: v_cmp_eq_i32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, {{v[0-9]+}}
20 ; SI-DAG: s_xor_b64 vcc, [[CMP0]], vcc
Dxor.ll43 ; SI-DAG: v_cmp_le_f32_e32 [[CMP0:vcc]], 0, {{v[0-9]+}}
45 ; SI: s_xor_b64 [[XOR:vcc]], [[CMP0]], [[CMP1]]
Dtrunc-cmp-constant.ll135 ; XSI: v_cmp_eq_i32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], [[TMP]], 0{{$}}
136 ; XSI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[CMP0]]
Dllvm.amdgcn.div.fmas.ll112 ; SI-DAG: v_cmp_eq_i32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}}
114 ; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.cpp13224 SDValue CMP0 = N0->getOperand(1); in CMPEQCombine() local
13229 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) in CMPEQCombine()
13232 SDValue CMP00 = CMP0->getOperand(0); in CMPEQCombine()
13233 SDValue CMP01 = CMP0->getOperand(1); in CMPEQCombine()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp27861 SDValue CMP0 = N0->getOperand(1); in combineCompareEqual() local
27866 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) in combineCompareEqual()
27869 SDValue CMP00 = CMP0->getOperand(0); in combineCompareEqual()
27870 SDValue CMP01 = CMP0->getOperand(1); in combineCompareEqual()