Searched refs:DefInst (Results 1 – 4 of 4) sorted by relevance
/external/llvm/lib/Target/AMDGPU/ |
D | SILowerI1Copies.cpp | 110 MachineInstr *DefInst = MRI.getUniqueVRegDef(Src.getReg()); in runOnMachineFunction() local 111 if (DefInst->getOpcode() == AMDGPU::S_MOV_B64) { in runOnMachineFunction() 112 if (DefInst->getOperand(1).isImm()) { in runOnMachineFunction() 115 int64_t Val = DefInst->getOperand(1).getImm(); in runOnMachineFunction()
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/external/llvm/lib/Transforms/Scalar/ |
D | EarlyCSE.cpp | 282 Instruction *DefInst; member 288 : DefInst(nullptr), Generation(0), MatchingId(-1), IsAtomic(false), in LoadValue() 292 : DefInst(Inst), Generation(Generation), MatchingId(MatchingId), in LoadValue() 637 if (InVal.DefInst != nullptr && in processNode() 644 Value *Op = getOrCreateResult(InVal.DefInst, Inst->getType()); in processNode() 647 << " to: " << *InVal.DefInst << '\n'); in processNode() 715 if (InVal.DefInst && in processNode() 716 InVal.DefInst == getOrCreateResult(Inst, InVal.DefInst->getType()) && in processNode()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonCopyToCombine.cpp | 400 MachineInstr *DefInst = LastDef[Reg]; in findPotentialNewifiableTFRs() local 401 if (!DefInst) in findPotentialNewifiableTFRs() 403 if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively)) in findPotentialNewifiableTFRs() 408 MachineBasicBlock::iterator It(DefInst); in findPotentialNewifiableTFRs() 419 PotentiallyNewifiableTFR.insert(DefInst); in findPotentialNewifiableTFRs()
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/external/swiftshader/third_party/subzero/src/ |
D | IceRegAlloc.cpp | 519 const Inst *DefInst = VMetadata->getFirstDefinitionSingleBlock(Iter.Cur); in findRegisterPreference() local 520 if (DefInst == nullptr) in findRegisterPreference() 523 assert(DefInst->getDest() == Iter.Cur); in findRegisterPreference() 525 DefInst->isVarAssign() && !VMetadata->isMultiDef(Iter.Cur); in findRegisterPreference() 526 FOREACH_VAR_IN_INST(SrcVar, *DefInst) { in findRegisterPreference()
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