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Searched refs:DestRC (Results 1 – 7 of 7) sorted by relevance

/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp38 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg() local
41 if (DestRC->getSize() != SrcRC->getSize()) in copyPhysReg()
45 if (DestRC == &NVPTX::Int1RegsRegClass) { in copyPhysReg()
47 } else if (DestRC == &NVPTX::Int16RegsRegClass) { in copyPhysReg()
49 } else if (DestRC == &NVPTX::Int32RegsRegClass) { in copyPhysReg()
52 } else if (DestRC == &NVPTX::Int64RegsRegClass) { in copyPhysReg()
55 } else if (DestRC == &NVPTX::Float32RegsRegClass) { in copyPhysReg()
58 } else if (DestRC == &NVPTX::Float64RegsRegClass) { in copyPhysReg()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp381 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
386 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
389 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
572 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in ListScheduleBottomUp() local
582 if (DestRC != RC) { in ListScheduleBottomUp()
584 if (!DestRC && !NewDef) in ListScheduleBottomUp()
591 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in ListScheduleBottomUp()
DScheduleDAGRRList.cpp972 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
977 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
980 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
1211 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in PickNodeToScheduleBottomUp() local
1221 if (DestRC != RC) { in PickNodeToScheduleBottomUp()
1223 if (!DestRC && !NewDef) in PickNodeToScheduleBottomUp()
1229 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in PickNodeToScheduleBottomUp()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp388 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
393 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
396 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
583 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in ListScheduleBottomUp() local
593 if (DestRC != RC) { in ListScheduleBottomUp()
595 if (!DestRC && !NewDef) in ListScheduleBottomUp()
602 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in ListScheduleBottomUp()
DScheduleDAGRRList.cpp1136 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
1141 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
1144 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
1449 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in PickNodeToScheduleBottomUp() local
1459 if (DestRC != RC) { in PickNodeToScheduleBottomUp()
1461 if (!DestRC && !NewDef) in PickNodeToScheduleBottomUp()
1467 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in PickNodeToScheduleBottomUp()
/external/llvm/lib/Target/AMDGPU/
DSIFoldOperands.cpp238 const TargetRegisterClass *DestRC in foldOperand() local
243 unsigned MovOp = TII->getMovOpcode(DestRC); in foldOperand()
DSIInstrInfo.cpp2718 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitUnaryOp() local
2719 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitUnaryOp()
2779 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitBinaryOp() local
2780 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitBinaryOp()