| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 1489 X86_INTRINSIC_DATA(avx512_mask_vfmadd_pd_128, FMA_OP_MASK, X86ISD::FMADD, 0),
1490 X86_INTRINSIC_DATA(avx512_mask_vfmadd_pd_256, FMA_OP_MASK, X86ISD::FMADD, 0),
1491 X86_INTRINSIC_DATA(avx512_mask_vfmadd_pd_512, FMA_OP_MASK, X86ISD::FMADD,
1493 X86_INTRINSIC_DATA(avx512_mask_vfmadd_ps_128, FMA_OP_MASK, X86ISD::FMADD, 0),
1494 X86_INTRINSIC_DATA(avx512_mask_vfmadd_ps_256, FMA_OP_MASK, X86ISD::FMADD, 0),
1495 X86_INTRINSIC_DATA(avx512_mask_vfmadd_ps_512, FMA_OP_MASK, X86ISD::FMADD,
1629 X86_INTRINSIC_DATA(avx512_mask3_vfmadd_pd_128, FMA_OP_MASK3, X86ISD::FMADD, 0),
1630 X86_INTRINSIC_DATA(avx512_mask3_vfmadd_pd_256, FMA_OP_MASK3, X86ISD::FMADD, 0),
1631 X86_INTRINSIC_DATA(avx512_mask3_vfmadd_pd_512, FMA_OP_MASK3, X86ISD::FMADD,
1633 X86_INTRINSIC_DATA(avx512_mask3_vfmadd_ps_128, FMA_OP_MASK3, X86ISD::FMADD, 0),
[all …]
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| D | X86ISelLowering.h | 474 FMADD, enumerator
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| D | X86InstrFragmentsSIMD.td | 469 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
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| D | X86ISelLowering.cpp | 22284 case X86ISD::FMADD: return "X86ISD::FMADD"; in getTargetNodeName()
29759 case X86ISD::FMADD: in combineFneg()
29769 return DAG.getNode(X86ISD::FMADD, DL, VT, Arg.getOperand(0), in combineFneg()
30229 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB; in combineFMA()
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| /external/valgrind/none/tests/ppc64/ |
| D | round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator
987 case FMADD: in check_double_guarded_arithmetic_op()
1000 fC = (op == FMADD || op == FNMADD ? s : -s)*A.dbl; in check_double_guarded_arithmetic_op()
1119 case FMADD: in check_double_guarded_arithmetic_op()
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| /external/valgrind/none/tests/ppc32/ |
| D | round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator
987 case FMADD: in check_double_guarded_arithmetic_op()
1000 fC = (op == FMADD || op == FNMADD ? s : -s)*A.dbl; in check_double_guarded_arithmetic_op()
1119 case FMADD: in check_double_guarded_arithmetic_op()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | README_ALTIVEC.txt | 25 Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
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| D | PPCInstrInfo.td | 1225 def FMADD : AForm_1<63, 29,
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| /external/valgrind/ |
| D | README.aarch64 | 146 FMADD/FMSUB/FNMADD/FNMSUB: generate and use the relevant fused
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| /external/v8/src/ppc/ |
| D | disasm-ppc.cc | 961 case FMADD: { in DecodeExt4()
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| D | constants-ppc.h | 1819 V(fmadd, FMADD, 0xFC00003A) \
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| D | assembler-ppc.cc | 2346 emit(EXT4 | FMADD | frt.code() * B21 | fra.code() * B16 | frb.code() * B11 | in fmadd()
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| D | simulator-ppc.cc | 2890 case FMADD: { in ExecuteExt4()
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| /external/llvm/lib/Target/PowerPC/ |
| D | README_ALTIVEC.txt | 25 Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
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| D | PPCInstrInfo.td | 2531 defm FMADD : AForm_1r<63, 29,
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| /external/v8/src/arm64/ |
| D | disasm-arm64.cc | 1050 FORMAT(FMADD, "fmadd"); in VisitFPDataProcessing3Source()
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| /external/vixl/src/aarch64/ |
| D | disasm-aarch64.cc | 1539 FORMAT(FMADD, "fmadd"); in VisitFPDataProcessing3Source()
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2077 ### FMADD ### subsection
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2632 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
|