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Searched refs:FMINNAN (Results 1 – 13 of 13) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h535 FMINNAN, FMAXNAN, enumerator
DBasicTTIImpl.h771 ISDs.push_back(ISD::FMINNAN); in getIntrinsicInstrCost()
DSelectionDAG.h1188 case ISD::FMINNAN:
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp155 case ISD::FMINNAN: return "fminnan"; in getOperationName()
DLegalizeVectorOps.cpp305 case ISD::FMINNAN: in LegalizeOp()
DSelectionDAGBuilder.cpp2784 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break; in visitSelect()
2789 else if (TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT)) in visitSelect()
2790 Opc = ISD::FMINNAN; in visitSelect()
2793 ISD::FMINNUM : ISD::FMINNAN; in visitSelect()
5209 I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT) in visitIntrinsicCall()
5210 ? ISD::FMINNAN in visitIntrinsicCall()
DLegalizeVectorTypes.cpp112 case ISD::FMINNAN: in ScalarizeVectorResult()
677 case ISD::FMINNAN: in SplitVectorResult()
2093 case ISD::FMINNAN: in WidenVectorResult()
DLegalizeFloatTypes.cpp1890 case ISD::FMINNAN: in PromoteFloatResult()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp90 setOperationAction(ISD::FMINNAN, T, Legal); in WebAssemblyTargetLowering()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp870 setOperationAction(ISD::FMINNAN, VT, Expand); in initActions()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td437 def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>;
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp294 setOperationAction(ISD::FMINNAN, MVT::f16, Promote); in AArch64TargetLowering()
386 setOperationAction(ISD::FMINNAN, Ty, Legal); in AArch64TargetLowering()
704 for (unsigned Opcode : {ISD::FMINNAN, ISD::FMAXNAN, in addTypeForNEON()
8558 return DAG.getNode(ISD::FMINNAN, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp1016 setOperationAction(ISD::FMINNAN, MVT::f32, Legal); in ARMTargetLowering()
1018 setOperationAction(ISD::FMINNAN, MVT::v2f32, Legal); in ARMTargetLowering()
1020 setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal); in ARMTargetLowering()
2992 ? ISD::FMINNAN : ISD::FMAXNAN; in LowerINTRINSIC_WO_CHAIN()