| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 452 FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 526 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
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| D | BasicTTIImpl.h | 791 ISDs.push_back(ISD::FNEARBYINT); in getIntrinsicInstrCost()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 306 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; in mightUseCTR()
352 Opcode = ISD::FNEARBYINT; break; in mightUseCTR()
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| D | PPCISelLowering.cpp | 153 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); in PPCTargetLowering()
477 setOperationAction(ISD::FNEARBYINT, VT, Expand); in PPCTargetLowering()
522 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
581 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in PPCTargetLowering()
808 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand); in PPCTargetLowering()
809 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand); in PPCTargetLowering()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 187 case ISD::FNEARBYINT: in LegalizeOp()
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| D | LegalizeFloatTypes.cpp | 80 case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break; in SoftenFloatResult()
863 case ISD::FNEARBYINT: ExpandFloatRes_FNEARBYINT(N, Lo, Hi); break; in ExpandFloatResult()
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| D | LegalizeVectorTypes.cpp | 80 case ISD::FNEARBYINT: in ScalarizeVectorResult()
456 case ISD::FNEARBYINT: in SplitVectorResult()
1307 case ISD::FNEARBYINT: in WidenVectorResult()
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| D | LegalizeDAG.cpp | 3375 case ISD::FNEARBYINT: in ExpandNode()
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| D | SelectionDAG.cpp | 5964 case ISD::FNEARBYINT: return "fnearbyint"; in getOperationName()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 166 case ISD::FNEARBYINT: return "fnearbyint"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 92 case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break; in SoftenFloatResult()
1032 case ISD::FNEARBYINT: ExpandFloatRes_FNEARBYINT(N, Lo, Hi); break; in ExpandFloatResult()
1878 case ISD::FNEARBYINT: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 321 case ISD::FNEARBYINT: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 86 case ISD::FNEARBYINT: in ScalarizeVectorResult()
644 case ISD::FNEARBYINT: in SplitVectorResult()
2162 case ISD::FNEARBYINT: in WidenVectorResult()
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| D | LegalizeDAG.cpp | 3876 case ISD::FNEARBYINT: in ConvertNodeToLibcall()
4224 case ISD::FNEARBYINT: in PromoteNode()
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| D | SelectionDAGBuilder.cpp | 5196 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; in visitIntrinsicCall()
6288 if (visitUnaryFloatCall(I, ISD::FNEARBYINT)) in visitCall()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 87 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 252 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom); in AMDGPUTargetLowering()
253 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom); in AMDGPUTargetLowering()
423 setOperationAction(ISD::FNEARBYINT, VT, Expand); in AMDGPUTargetLowering()
716 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG); in LowerOperation()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 930 setOperationAction(ISD::FNEARBYINT, VT, Expand); in initActions()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 278 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote); in AArch64TargetLowering()
321 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand); in AArch64TargetLowering()
353 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand); in AArch64TargetLowering()
379 setOperationAction(ISD::FNEARBYINT, Ty, Legal); in AArch64TargetLowering()
532 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand); in AArch64TargetLowering()
623 setOperationAction(ISD::FNEARBYINT, Ty, Legal); in AArch64TargetLowering()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 382 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 452 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 513 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); in ARMTargetLowering()
530 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand); in ARMTargetLowering()
547 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand); in ARMTargetLowering()
676 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); in ARMTargetLowering()
992 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); in ARMTargetLowering()
1006 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); in ARMTargetLowering()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 362 setOperationAction(ISD::FNEARBYINT, VT, Legal); in SystemZTargetLowering()
401 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in SystemZTargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1948 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR, in HexagonTargetLowering()
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