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Searched refs:FP_TO_SINT (Results 1 – 25 of 55) sorted by relevance

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/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp153 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
155 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
157 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
171 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
173 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
175 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
188 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
190 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 }, in getCastInstrCost()
192 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
194 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp256 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
257 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
258 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
264 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 }, in getCastInstrCost()
265 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
266 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 }, in getCastInstrCost()
272 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
273 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
278 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
279 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
[all …]
/external/llvm/test/CodeGen/X86/
Davx-fp2int.ll3 ;; Check that FP_TO_SINT and FP_TO_UINT generate convert with truncate
Dhalf.ll123 ; FP_TO_UINT is expanded using FP_TO_SINT
/external/llvm/test/CodeGen/AMDGPU/
Dfcmp.ll19 ; SET* + FP_TO_SINT
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h587 ISD::FP_TO_SINT, 0),
589 ISD::FP_TO_SINT, 0),
591 ISD::FP_TO_SINT, ISD::FP_TO_SINT),
593 ISD::FP_TO_SINT, 0),
595 ISD::FP_TO_SINT, 0),
597 ISD::FP_TO_SINT, ISD::FP_TO_SINT),
611 ISD::FP_TO_SINT, 0),
613 ISD::FP_TO_SINT, 0),
615 ISD::FP_TO_SINT, ISD::FP_TO_SINT),
617 ISD::FP_TO_SINT, 0),
[all …]
DREADME-FPStack.txt50 FP_TO_SINT when the source operand is already in memory.
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp299 case ISD::FP_TO_SINT: in LegalizeOp()
392 case ISD::FP_TO_SINT: in Promote()
394 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT); in Promote()
478 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) { in PromoteFP_TO_INT()
479 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
DLegalizeFloatTypes.cpp759 case ISD::FP_TO_SINT: in SoftenFloatOperand()
887 bool Signed = N->getOpcode() == ISD::FP_TO_SINT; in SoftenFloatOp_FP_TO_XINT()
1509 case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break; in ExpandFloatOperand()
1616 return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res); in ExpandFloatOp_FP_TO_SINT()
1641 DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, in ExpandFloatOp_FP_TO_UINT()
1648 DAG.getNode(ISD::FP_TO_SINT, dl, in ExpandFloatOp_FP_TO_UINT()
1747 case ISD::FP_TO_SINT: in PromoteFloatOperand()
DSelectionDAGDumper.cpp256 case ISD::FP_TO_SINT: return "fp_to_sint"; in getOperationName()
DLegalizeDAG.cpp2531 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { in PromoteLegalFP_TO_INT()
2532 OpToUse = ISD::FP_TO_SINT; in PromoteLegalFP_TO_INT()
2932 case ISD::FP_TO_SINT: in ExpandNode()
2948 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); in ExpandNode()
2950 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, in ExpandNode()
4050 case ISD::FP_TO_SINT: in PromoteNode()
4052 Node->getOpcode() == ISD::FP_TO_SINT, dl); in PromoteNode()
DLegalizeVectorTypes.cpp89 case ISD::FP_TO_SINT: in ScalarizeVectorResult()
440 case ISD::FP_TO_SINT: in ScalarizeVectorOperand()
648 case ISD::FP_TO_SINT: in SplitVectorResult()
1484 case ISD::FP_TO_SINT: in SplitVectorOperand()
2138 case ISD::FP_TO_SINT: in WidenVectorResult()
3097 case ISD::FP_TO_SINT: in WidenVectorOperand()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h384 FP_TO_SINT, enumerator
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DREADME-FPStack.txt50 FP_TO_SINT when the source operand is already in memory.
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h448 FP_TO_SINT, enumerator
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp587 case ISD::FP_TO_SINT: Res = SoftenFloatOp_FP_TO_SINT(N); break; in SoftenFloatOperand()
1267 case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break; in ExpandFloatOperand()
1364 return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res); in ExpandFloatOp_FP_TO_SINT()
1388 DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, in ExpandFloatOp_FP_TO_UINT()
1394 DAG.getNode(ISD::FP_TO_SINT, dl, in ExpandFloatOp_FP_TO_UINT()
DLegalizeVectorOps.cpp170 case ISD::FP_TO_SINT: in LegalizeOp()
DLegalizeVectorTypes.cpp83 case ISD::FP_TO_SINT: in ScalarizeVectorResult()
460 case ISD::FP_TO_SINT: in SplitVectorResult()
985 case ISD::FP_TO_SINT: in SplitVectorOperand()
1285 case ISD::FP_TO_SINT: in WidenVectorResult()
2037 case ISD::FP_TO_SINT: in WidenVectorOperand()
DLegalizeDAG.cpp2705 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { in PromoteLegalFP_TO_INT()
2706 OpToUse = ISD::FP_TO_SINT; in PromoteLegalFP_TO_INT()
3151 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); in ExpandNode()
3152 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, in ExpandNode()
3869 case ISD::FP_TO_SINT: in PromoteNode()
3871 Node->getOpcode() == ISD::FP_TO_SINT, dl); in PromoteNode()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp325 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in SPUTargetLowering()
327 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); in SPUTargetLowering()
331 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SPUTargetLowering()
333 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand); in SPUTargetLowering()
335 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Expand); in SPUTargetLowering()
383 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SPUTargetLowering()
2470 (Op.getOpcode() == ISD::FP_TO_SINT) in LowerFP_TO_INT()
2819 case ISD::FP_TO_SINT: in LowerOperation()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp260 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
370 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
388 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
394 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
515 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in PPCTargetLowering()
646 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal); in PPCTargetLowering()
701 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal); in PPCTargetLowering()
751 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal); in PPCTargetLowering()
6389 Op.getOpcode() == ISD::FP_TO_SINT in LowerFP_TO_INTForReuse()
6395 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) && in LowerFP_TO_INTForReuse()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaISelLowering.cpp86 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AlphaTargetLowering()
629 case ISD::FP_TO_SINT: { in LowerOperation()
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp125 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in R600TargetLowering()
196 setTargetDAGCombine(ISD::FP_TO_SINT); in R600TargetLowering()
843 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
1969 case ISD::FP_TO_SINT: { in PerformDAGCombine()
DAMDGPUISelLowering.cpp330 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AMDGPUTargetLowering()
367 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in AMDGPUTargetLowering()
721 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); in LowerOperation()
1255 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
2061 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL, in LowerFP64_TO_INT()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp2023 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in HexagonTargetLowering()
2024 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in HexagonTargetLowering()
2025 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); in HexagonTargetLowering()
2038 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand); in HexagonTargetLowering()
2039 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand); in HexagonTargetLowering()

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