| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTLSDynamicCall.cpp | 72 unsigned InReg = MI->getOperand(1).getReg(); in processBlock() local
76 const unsigned OrigRegs[] = {OutReg, InReg, GPR3}; in processBlock()
106 .addReg(InReg); in processBlock()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetCallingConv.h | 27 static const uint64_t InReg = 1ULL<<2; ///< Passed in register member
56 bool isInReg() const { return Flags & InReg; } in isInReg()
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| /external/clang/include/clang/CodeGen/ |
| D | CGFunctionInfo.h | 96 bool InReg : 1; // isDirect() || isExtend() || isIndirect() variable
113 : TheKind(K), PaddingInReg(false), InReg(false) { in ABIArgInfo()
119 TheKind(Direct), PaddingInReg(false), InReg(false) {} in ABIArgInfo()
300 return InReg; in getInReg()
305 InReg = IR; in setInReg()
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| /external/llvm/include/llvm/Target/ |
| D | TargetCallingConv.h | 32 static const uint64_t InReg = 1ULL<<2; ///< Passed in register member
76 bool isInReg() const { return Flags & InReg; } in isInReg()
|
| /external/swiftshader/third_party/LLVM/include/llvm/ |
| D | Attributes.h | 40 const Attributes InReg = 1<<3; ///< Force argument to be passed in register variable
102 ByVal | InReg | Nest | StructRet,
|
| /external/mesa3d/src/amd/common/ |
| D | ac_llvm_helper.cpp | 54 AS.hasAttribute(ArgNo + 1, llvm::Attribute::InReg); in ac_is_sgpr_param()
|
| /external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
| D | Attributes.gen | 14 InReg,
71 .Case("inreg", Attribute::InReg)
204 return llvm::Attribute::InReg;
|
| /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
| D | Attributes.gen | 14 InReg,
71 .Case("inreg", Attribute::InReg)
204 return llvm::Attribute::InReg;
|
| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Attributes.gen | 14 InReg,
71 .Case("inreg", Attribute::InReg)
204 return llvm::Attribute::InReg;
|
| /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
| D | Attributes.gen | 14 InReg,
71 .Case("inreg", Attribute::InReg)
204 return llvm::Attribute::InReg;
|
| /external/swiftshader/third_party/llvm-subzero/include/llvm/IR/ |
| D | Attributes.inc | 14 InReg,
71 .Case("inreg", Attribute::InReg)
204 return llvm::Attribute::InReg;
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | VirtRegRewriter.cpp | 1808 unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); in InsertRestores() local
1809 if (InReg == Phys) { in InsertRestores()
1818 << TRI->getName(InReg) << " for " << PrintReg(VirtReg) in InsertRestores()
1827 } else if (InReg && InReg != Phys) { in InsertRestores()
1834 << TRI->getName(InReg) << " for " << PrintReg(VirtReg) in InsertRestores()
1847 .addReg(InReg, RegState::Kill); in InsertRestores()
2359 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) { in RewriteMBB() local
2361 if (DestReg != InReg) { in RewriteMBB()
2366 .addReg(InReg, RegState::Kill); in RewriteMBB()
2377 Spills.disallowClobberPhysReg(InReg); in RewriteMBB()
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| /external/llvm/include/llvm/CodeGen/ |
| D | FastISel.h | 104 IsInReg = Call.paramHasAttr(0, Attribute::InReg); in setCallee()
128 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUTargetTransformInfo.cpp | 297 if (F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::InReg) || in isArgPassedInSGPR()
|
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| D | Attributes.cpp | 43 if (Attrs & Attribute::InReg) in getAsString()
|
| /external/clang/lib/CodeGen/ |
| D | TargetInfo.cpp | 924 bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
1430 bool &InReg, in shouldAggregateUseDirect() argument
1439 InReg = !IsMCUABI; in shouldAggregateUseDirect()
1523 bool InReg; in classifyArgumentType() local
1524 if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) { in classifyArgumentType()
1528 if (InReg) in classifyArgumentType()
1572 bool InReg = shouldPrimitiveUseInReg(Ty, State); in classifyArgumentType() local
1575 if (InReg) in classifyArgumentType()
1580 if (InReg) in classifyArgumentType()
6852 bool InReg = shouldUseInReg(Ty, State); in classifyArgumentType() local
[all …]
|
| D | CGCall.cpp | 1815 RetAttrs.addAttribute(llvm::Attribute::InReg); in ConstructAttributeList()
1858 SRETAttrs.addAttribute(llvm::Attribute::InReg); in ConstructAttributeList()
1884 llvm::Attribute::InReg)); in ConstructAttributeList()
1905 Attrs.addAttribute(llvm::Attribute::InReg); in ConstructAttributeList()
1910 Attrs.addAttribute(llvm::Attribute::InReg); in ConstructAttributeList()
|
| /external/llvm/include/llvm/IR/ |
| D | Attributes.td | 62 def InReg : EnumAttr<"inreg">;
|
| /external/llvm/lib/IR/ |
| D | Attributes.cpp | 253 if (hasAttribute(Attribute::InReg)) in getAsString()
477 case Attribute::InReg: return 1 << 3; in getAttrMask()
|
| /external/llvm/lib/Target/X86/ |
| D | X86WinEHState.cpp | 415 Call->addAttribute(1, Attribute::InReg); in generateLSDAInEAXThunk()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 984 unsigned InReg = It->second; in getValue() local
985 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); in getValue()
1122 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); in getValueImpl() local
1123 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); in getValueImpl()
1199 if (F->paramHasAttr(0, Attribute::InReg)) in visitRet()
5191 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); in LowerCallTo()
5236 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), in LowerCallTo()
6580 if (F.paramHasAttr(Idx, Attribute::InReg)) in LowerArguments()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86FastISel.cpp | 1592 if (CS.paramHasAttr(AttrInd, Attribute::InReg)) in DoSelectCall()
1859 if (CS.paramHasAttr(0, Attribute::InReg)) in DoSelectCall()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 85 IsInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg); in setAttributes()
864 Attrs.push_back(Attribute::InReg); in getReturnAttrs()
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| D | SelectionDAGBuilder.cpp | 1041 unsigned InReg = It->second; in getCopyFromRegs() local
1043 DAG.getDataLayout(), InReg, Ty); in getCopyFromRegs()
1231 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); in getValueImpl() local
1232 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg, in getValueImpl()
1454 Attribute::InReg); in visitRet()
2065 if (Fn->hasAttribute(1, Attribute::AttrKind::InReg)) in visitSPDescriptorParent()
7471 Attrs.push_back(Attribute::InReg); in getReturnAttrs()
7876 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg)) in LowerArguments()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2342 if (CS.paramHasAttr(AttrInd, Attribute::InReg) || in SelectCall()
3011 if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) || in fastLowerArguments()
|