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Searched refs:MRM3r (Results 1 – 23 of 23) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h215 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
491 case X86II::MRM2r: case X86II::MRM3r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp579 case X86II::MRM2r: case X86II::MRM3r: in EmitVEXOpcodePrefix()
965 case X86II::MRM2r: case X86II::MRM3r: in EncodeInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrShiftRotate.td326 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
328 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
331 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
334 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
336 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
339 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
342 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
344 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
347 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
350 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
[all …]
DX86InstrSystem.td226 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
463 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$dst),
465 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$dst),
DX86InstrArithmetic.td312 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
316 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
320 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
324 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
1102 defm SBB : ArithBinOp_RFF<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, X86sbb_flag,
DX86CodeEmitter.cpp902 case X86II::MRM2r: case X86II::MRM3r: in emitInstruction()
DX86InstrFormats.td26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
DX86InstrSSE.td3553 def VPSRLDQri : PDIi8<0x73, MRM3r,
3603 def PSRLDQri : PDIi8<0x73, MRM3r,
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td377 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
379 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
382 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
385 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
387 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
390 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
393 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
395 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
398 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
401 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
[all …]
DX86InstrFPStack.td293 def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">;
389 def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RST:$op),
397 def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RST:$op),
541 def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op", IIC_FST>;
DX86InstrSystem.td254 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
591 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
594 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
DX86InstrArithmetic.td377 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
381 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
385 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
389 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
1207 defm SBB : ArithBinOp_RFF<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, X86sbb_flag,
DX86InstrInfo.td2224 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2225 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2400 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
DX86InstrFormats.td31 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
DX86InstrSSE.td4084 def VPSRLDQri : PDIi8<0x73, MRM3r,
4134 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4179 def PSRLDQri : PDIi8<0x73, MRM3r,
DX86InstrAVX512.td7675 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
/external/swiftshader/third_party/LLVM/utils/TableGen/
DX86RecognizableInstr.cpp51 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
730 case X86Local::MRM3r: in emitInstructionSpecifier()
822 case X86Local::MRM3r: in emitDecodePath()
911 case X86Local::MRM3r: in emitDecodePath()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h295 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
686 case X86II::MRM2r: case X86II::MRM3r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp870 case X86II::MRM2r: case X86II::MRM3r: in EmitVEXOpcodePrefix()
1021 case X86II::MRM2r: case X86II::MRM3r: in DetermineREXPrefix()
1356 case X86II::MRM2r: case X86II::MRM3r: in encodeInstruction()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
718 case X86Local::MRM3r: in emitInstructionSpecifier()
853 case X86Local::MRM2r: case X86Local::MRM3r: in emitDecodePath()
/external/llvm/test/TableGen/
DTargetInstrInfo.td53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
/external/swiftshader/third_party/LLVM/test/TableGen/
DTargetInstrInfo.td53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
/external/llvm/docs/
DWritingAnLLVMBackend.rst1819 case X86II::MRM2r: case X86II::MRM3r: // a REGISTER r/m operand and