| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenInstrInfo.inc | 4206 …{ 22, 6, 1, 0, 0, "ACQUIRE_MOV16rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x0ULL, NULL, NULL,…
4207 …{ 23, 6, 1, 0, 0, "ACQUIRE_MOV32rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x0ULL, NULL, NULL,…
4208 …{ 24, 6, 1, 0, 0, "ACQUIRE_MOV64rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x0ULL, NULL, NULL,…
4209 …{ 25, 6, 1, 0, 0, "ACQUIRE_MOV8rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x0ULL, NULL, NULL, …
4211 …{ 27, 6, 0, 0, 0, "ADC16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10200c05aULL, ImplicitLis…
4212 …{ 28, 6, 0, 0, 0, "ADC16mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600405aULL, ImplicitLi…
4213 …{ 29, 6, 0, 0, 0, "ADC16mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x22000044ULL, ImplicitList…
4216 …{ 32, 7, 1, 0, 0, "ADC16rm", 0|(1<<MCID::MayLoad), 0x26000046ULL, ImplicitList1, ImplicitList1, Op…
4220 …{ 36, 6, 0, 0, 0, "ADC32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10201401aULL, ImplicitLis…
4221 …{ 37, 6, 0, 0, 0, "ADC32mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600401aULL, ImplicitLi…
[all …]
|
| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCInstrDesc.h | 112 MayLoad, enumerator
411 return Flags & (1 << MCID::MayLoad); in mayLoad()
|
| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 113 MayLoad, enumerator
350 bool mayLoad() const { return Flags & (1 << MCID::MayLoad); } in mayLoad()
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrInfo.td | 518 class MayLoad {
789 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, II_LB>, MayLoad{
799 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, II_LBU>, MayLoad {
808 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, II_LH>, MayLoad{
818 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, II_LHU>, MayLoad {
845 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, II_LW>, MayLoad{
853 def LwRxSpImmX16: FEXT_RRI16_mem_ins<0b10010, "lw", mem16sp, II_LW>, MayLoad;
855 def LwRxPcTcp16: FRI16_TCP_ins<0b10110, "lw", II_LW>, MayLoad;
857 def LwRxPcTcpX16: FEXT_RI16_TCP_ins<0b10110, "lw", II_LW>, MayLoad;
961 "", [], II_RESTORE >, MayLoad {
[all …]
|
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenDAGPatterns.cpp | 2471 bool &MayStore, bool &MayLoad, in InferFromPattern() argument
2475 MayStore = MayLoad = IsBitcast = HasSideEffects = IsVariadic = false; in InferFromPattern()
2478 InstAnalyzer(CDP, MayStore, MayLoad, IsBitcast, HasSideEffects, IsVariadic) in InferFromPattern()
2496 if (MayLoad) in InferFromPattern()
2501 MayLoad = true; in InferFromPattern()
2824 bool MayStore, MayLoad, IsBitcast, HasSideEffects, IsVariadic; in InferInstructionFlags() local
2825 InferFromPattern(InstInfo, MayStore, MayLoad, IsBitcast, in InferInstructionFlags()
2828 InstInfo.mayLoad = MayLoad; in InferInstructionFlags()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 1214 bool MayLoad = FirstMI.mayLoad(); in findMatchingInsn() local
1305 if (MayLoad && Reg == getLdStRegOp(MI).getReg()) { in findMatchingInsn()
1327 !(MayLoad && UsedRegs[getLdStRegOp(FirstMI).getReg()]) && in findMatchingInsn()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 611 return hasProperty(MCID::MayLoad, Type);
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoV4.td | 4003 // because the SDNode ISD::PREFETCH has properties MayLoad and MayStore.
|