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Searched refs:OPERAND_REGISTER (Results 1 – 6 of 6) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenInstrInfo.inc3927 …= { { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP32RegClassID, 0, 0, MCOI::OP…
3928 …= { { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP64RegClassID, 0, 0, MCOI::OP…
3929 …= { { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP80RegClassID, 0, 0, MCOI::OP…
3930 static const MCOperandInfo OperandInfo11[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER
3931 static const MCOperandInfo OperandInfo12[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER
3932 static const MCOperandInfo OperandInfo13[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER
3933 static const MCOperandInfo OperandInfo14[] = { { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }…
3935 …RY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, };
3936 …RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIE…
3937 …RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIE…
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/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInstrDesc.h46 OPERAND_REGISTER, enumerator
/external/llvm/lib/Target/WebAssembly/Disassembler/
DWebAssemblyDisassembler.cpp105 case MCOI::OPERAND_REGISTER: { in getInstruction()
/external/llvm/include/llvm/MC/
DMCInstrDesc.h47 OPERAND_REGISTER = 2, enumerator
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp1675 case MCOI::OPERAND_REGISTER: in verifyInstruction()
/external/llvm/include/llvm/Target/
DTarget.td683 string OperandType = "OPERAND_REGISTER";