Searched refs:OP_STORE (Results 1 – 14 of 14) sorted by relevance
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_target_gm107.cpp | 199 case OP_STORE: in getLatency()
299 case OP_STORE: in getReadLatency()
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| D | nv50_ir_target_nv50.cpp | 127 OP_STORE, OP_WRSV, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT, in initOpInfo()
278 i->op != OP_EXPORT && i->op != OP_STORE); in insnCanLoad()
396 if (i->op == OP_LOAD || i->op == OP_STORE) { in insnCanLoadOffset()
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| D | nv50_ir_target_nvc0.cpp | 174 OP_STORE, OP_WRSV, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT, in initOpInfo()
323 i->op != OP_EXPORT && i->op != OP_STORE); in insnCanLoad()
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| D | nv50_ir_print.cpp | 590 case OP_STORE: in print()
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| D | nv50_ir_build_util.cpp | 540 up->mkStore(OP_STORE, stTy, static_cast<Symbol *>(sym), ptr, value); in store()
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| D | nv50_ir_ra.cpp | 1630 st = new_Instruction(func, OP_STORE, ty); in spill()
1644 Instruction *s = new_Instruction(func, OP_STORE, TYPE_U32); in spill()
2270 if (i->op == OP_EXPORT || i->op == OP_STORE) { in visit()
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| D | nv50_ir.h | 51 OP_STORE, enumerator
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| D | nv50_ir_lowering_nvc0.cpp | 1257 bld.mkStore(OP_STORE, TYPE_U32, atom->getSrc(0)->asSym(), in handleSharedATOMNVE4()
1353 bld.mkStore(OP_STORE, TYPE_U32, atom->getSrc(0)->asSym(), in handleSharedATOM()
2710 case OP_STORE: in visit()
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| D | nv50_ir_peephole.cpp | 66 if (op == OP_STORE || in isDead()
2729 if (ldst->op == OP_STORE || ldst->op == OP_EXPORT) { in runOpt()
2988 ((insn->op != OP_LOAD && insn->op != OP_STORE && insn->op != OP_ATOM) || in visit()
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| D | nv50_ir_emit_nv50.cpp | 1872 case OP_STORE: in emitInstruction()
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| D | nv50_ir_emit_gk110.cpp | 2399 case OP_STORE: in emitInstruction()
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| D | nv50_ir_emit_nvc0.cpp | 2597 case OP_STORE: in emitInstruction()
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| D | nv50_ir_emit_gm107.cpp | 3251 case OP_STORE: in emitInstruction()
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| D | nv50_ir_from_tgsi.cpp | 2649 Instruction *st = mkStore(OP_STORE, TYPE_U32, sym, off, fetchSrc(1, c)); in handleSTORE()
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