| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenFastISel.inc | 18 unsigned FastEmit_ISD_ANY_EXTEND_MVT_i8_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
19 return FastEmitInst_r(X86::MOVZX32rr8, X86::GR32RegisterClass, Op0, Op0IsKill);
22 unsigned FastEmit_ISD_ANY_EXTEND_MVT_i8_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
23 return FastEmitInst_r(X86::MOVZX64rr8, X86::GR64RegisterClass, Op0, Op0IsKill);
26 unsigned FastEmit_ISD_ANY_EXTEND_MVT_i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
28 case MVT::i32: return FastEmit_ISD_ANY_EXTEND_MVT_i8_MVT_i32_r(Op0, Op0IsKill);
29 case MVT::i64: return FastEmit_ISD_ANY_EXTEND_MVT_i8_MVT_i64_r(Op0, Op0IsKill);
34 unsigned FastEmit_ISD_ANY_EXTEND_MVT_i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
37 return FastEmitInst_r(X86::MOVZX64rr16, X86::GR64RegisterClass, Op0, Op0IsKill);
40 unsigned FastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | FastISel.h | 168 unsigned Op0, bool Op0IsKill);
177 unsigned Op0, bool Op0IsKill,
187 unsigned Op0, bool Op0IsKill,
197 unsigned Op0, bool Op0IsKill,
207 unsigned Op0, bool Op0IsKill,
217 unsigned Op0, bool Op0IsKill,
247 unsigned Op0, bool Op0IsKill);
254 unsigned Op0, bool Op0IsKill,
262 unsigned Op0, bool Op0IsKill,
271 unsigned Op0, bool Op0IsKill,
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| /external/llvm/include/llvm/CodeGen/ |
| D | FastISel.h | 346 bool Op0IsKill);
351 bool Op0IsKill, unsigned Op1, bool Op1IsKill);
357 bool Op0IsKill, uint64_t Imm);
363 bool Op0IsKill, const ConstantFP *FPImm);
369 unsigned Op0, bool Op0IsKill, unsigned Op1,
377 unsigned fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill,
399 bool Op0IsKill);
405 bool Op0IsKill, unsigned Op1, bool Op1IsKill);
411 bool Op0IsKill, unsigned Op1, bool Op1IsKill,
418 bool Op0IsKill, uint64_t Imm);
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 366 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); in SelectBinaryOp() local
381 Op0IsKill, Imm, VT.getSimpleVT()); in SelectBinaryOp()
392 ISDOpcode, Op0, Op0IsKill, CF); in SelectBinaryOp()
410 Op0, Op0IsKill, in SelectBinaryOp()
724 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); in SelectBitCast() local
742 ISD::BITCAST, Op0, Op0IsKill); in SelectBitCast()
1063 unsigned Op0, bool Op0IsKill, in FastEmit_ri_() argument
1082 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); in FastEmit_ri_()
1094 Op0, Op0IsKill, in FastEmit_ri_()
1113 unsigned Op0, bool Op0IsKill) { in FastEmitInst_r() argument
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 428 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); in selectBinaryOp() local
449 Op0IsKill, Imm, VT.getSimpleVT()); in selectBinaryOp()
461 ISDOpcode, Op0, Op0IsKill, CF); in selectBinaryOp()
476 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill); in selectBinaryOp()
1301 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); in selectBitCast() local
1318 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); in selectBitCast()
1743 bool Op0IsKill, uint64_t Imm, MVT ImmType) { in fastEmit_ri_() argument
1761 unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); in fastEmit_ri_()
1782 return fastEmit_rr(VT, VT, Opcode, Op0, Op0IsKill, MaterialReg, IsImmKill); in fastEmit_ri_()
1817 bool Op0IsKill) { in fastEmitInst_r() argument
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 113 unsigned Op0, bool Op0IsKill);
116 unsigned Op0, bool Op0IsKill,
120 unsigned Op0, bool Op0IsKill,
125 unsigned Op0, bool Op0IsKill,
129 unsigned Op0, bool Op0IsKill,
133 unsigned Op0, bool Op0IsKill,
144 unsigned Op0, bool Op0IsKill,
289 unsigned Op0, bool Op0IsKill) { in FastEmitInst_r() argument
295 .addReg(Op0, Op0IsKill * RegState::Kill)); in FastEmitInst_r()
298 .addReg(Op0, Op0IsKill * RegState::Kill)); in FastEmitInst_r()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 193 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
211 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
213 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
215 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
217 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
219 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
221 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
223 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
225 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
227 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 106 unsigned Op0, bool Op0IsKill);
109 unsigned Op0, bool Op0IsKill,
113 unsigned Op0, bool Op0IsKill,
117 unsigned Op0, bool Op0IsKill,
280 unsigned Op0, bool Op0IsKill) { in fastEmitInst_r() argument
289 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
292 .addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
302 unsigned Op0, bool Op0IsKill, in fastEmitInst_rr() argument
315 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rr()
319 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rr()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 117 unsigned Op0, bool Op0IsKill,
121 unsigned Op0, bool Op0IsKill);
124 unsigned Op0, bool Op0IsKill,
2304 unsigned Op0, bool Op0IsKill, in fastEmitInst_ri() argument
2316 Op0, Op0IsKill, Imm); in fastEmitInst_ri()
2324 unsigned Op0, bool Op0IsKill) { in fastEmitInst_r() argument
2329 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill); in fastEmitInst_r()
2337 unsigned Op0, bool Op0IsKill, in fastEmitInst_rr() argument
2343 return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill, in fastEmitInst_rr()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 180 unsigned Op0, bool Op0IsKill,
187 unsigned Op0, bool Op0IsKill, uint64_t imm1, in fastEmitInst_riir() argument
1868 unsigned Op0, bool Op0IsKill, in fastEmitInst_rr() argument
1882 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr()
1889 return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1, in fastEmitInst_rr()
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