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Searched refs:OpRC (Results 1 – 3 of 3) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/CodeGen/
DMachineRegisterInfo.cpp82 const TargetRegisterClass *OpRC = in recomputeRegClass() local
84 if (OpRC) in recomputeRegClass()
85 NewRC = TRI->getCommonSubClass(NewRC, OpRC); in recomputeRegClass()
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp2236 const TargetRegisterClass *OpRC = in legalizeOperands() local
2238 if (RI.hasVGPRs(OpRC)) { in legalizeOperands()
2239 VRC = OpRC; in legalizeOperands()
2241 SRC = OpRC; in legalizeOperands()
2290 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
2291 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands()
2292 if (VRC == OpRC) in legalizeOperands()
3003 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); in findUsedSGPR() local
3004 bool IsRequiredSGPR = RI.isSGPRClass(OpRC); in findUsedSGPR()
/external/llvm/lib/CodeGen/
DMachineInstr.cpp1246 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
1252 if (OpRC) in getRegClassConstraintEffect()
1253 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
1256 } else if (OpRC) in getRegClassConstraintEffect()
1257 CurRC = TRI->getCommonSubClass(CurRC, OpRC); in getRegClassConstraintEffect()