Searched refs:POST_INC (Results 1 – 18 of 18) sorted by relevance
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 675 POST_INC, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 811 POST_INC, enumerator
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 86 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
87 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
965 AM = ISD::POST_INC; in getPostIndexedAddressParts()
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| D | MSP430ISelDAGToDAG.cpp | 304 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD) in isValidIndexedLoad()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelDAGToDAG.cpp | 301 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD) in isValidIndexedLoad()
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| D | MSP430ISelLowering.cpp | 77 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
78 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
1107 AM = ISD::POST_INC; in getPostIndexedAddressParts()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 730 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetReg()
766 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImmPre()
786 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImm()
859 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode3Offset()
943 if (AM != ISD::POST_INC) in SelectAddrMode6Offset()
1263 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm8Offset()
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| D | ARMISelLowering.cpp | 8386 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; in getPostIndexedAddressParts()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 367 case ISD::POST_INC: return "<post-inc>"; in getIndexedModeName()
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| D | DAGCombiner.cpp | 9897 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && in CombineToPostIndexedLoadStore()
9905 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && in CombineToPostIndexedLoadStore()
10022 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB); in SplitIndexingFromLoad()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 905 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetReg()
941 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImmPre()
961 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImm()
1040 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode3Offset()
1135 if (AM != ISD::POST_INC) in SelectAddrMode6Offset()
1368 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm8Offset()
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| D | ARMISelLowering.cpp | 11624 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; in getPostIndexedAddressParts()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 948 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; in getPostIndexedAddressParts()
2067 setIndexedLoadAction(ISD::POST_INC, LSXTy, Legal); in HexagonTargetLowering()
2068 setIndexedStoreAction(ISD::POST_INC, LSXTy, Legal); in HexagonTargetLowering()
2073 setIndexedLoadAction(ISD::POST_INC, VT, Legal); in HexagonTargetLowering()
2074 setIndexedStoreAction(ISD::POST_INC, VT, Legal); in HexagonTargetLowering()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 739 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
745 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 912 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
918 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 6012 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && in CombineToPostIndexedLoadStore()
6020 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && in CombineToPostIndexedLoadStore()
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| D | SelectionDAG.cpp | 6134 case ISD::POST_INC: in getIndexedModeName()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 10049 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC; in getPostIndexedAddressParts()
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