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Searched refs:PPCSubTarget (Results 1 – 11 of 11) sorted by relevance

/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp69 const PPCSubtarget *PPCSubTarget; member in __anon0e9c87610111::PPCDAGToDAGISel
79 PPCSubTarget = &MF.getSubtarget<PPCSubtarget>(); in runOnMachineFunction()
80 PPCLowering = PPCSubTarget->getTargetLowering(); in runOnMachineFunction()
83 if (!PPCSubTarget->isSVR4ABI()) in runOnMachineFunction()
201 const TargetRegisterInfo *TRI = PPCSubTarget->getRegisterInfo(); in SelectInlineAsmMemoryOperand()
276 const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo(); in InsertVRSaveCode()
312 const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo(); in getGlobalBaseReg()
320 if (PPCSubTarget->isTargetELF()) { in getGlobalBaseReg()
2084 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD; in SelectCC()
2268 if (!PPCSubTarget->useCRBits() && in trySETCC()
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DPPCFastISel.cpp90 const PPCSubtarget *PPCSubTarget; member in __anonaa7ccd940111::PPCFastISel
100 PPCSubTarget(&FuncInfo.MF->getSubtarget<PPCSubtarget>()), in PPCFastISel()
102 TII(*PPCSubTarget->getInstrInfo()), in PPCFastISel()
103 TLI(*PPCSubTarget->getTargetLowering()), in PPCFastISel()
821 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits()) in PPCEmitCmp()
981 Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4; in PPCMoveToFPReg()
982 } else if (PPCSubTarget->hasLFIWAX()) { in PPCMoveToFPReg()
984 Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4; in PPCMoveToFPReg()
1025 if (!IsSigned && !PPCSubTarget->hasFPCVT()) in SelectIToFP()
1033 if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT()) in SelectIToFP()
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DPPCInstrHTM.td17 def HasHTM : Predicate<"PPCSubTarget->hasHTM()">;
DPPCInstrInfo.td779 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
780 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
781 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
782 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
783 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
784 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
785 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
786 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
787 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
788 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
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DPPCInstrAltivec.td339 def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">;
1016 def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">;
1017 def HasP8Crypto : Predicate<"PPCSubTarget->hasP8Crypto()">;
1218 def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">;
DPPCInstrVSX.td92 def HasVSX : Predicate<"PPCSubTarget->hasVSX()">;
93 def IsLittleEndian : Predicate<"PPCSubTarget->isLittleEndian()">;
94 def IsBigEndian : Predicate<"!PPCSubTarget->isLittleEndian()">;
1040 def HasP8Vector : Predicate<"PPCSubTarget->hasP8Vector()">;
1041 def HasDirectMove : Predicate<"PPCSubTarget->hasDirectMove()">;
1830 def HasP9Vector : Predicate<"PPCSubTarget->hasP9Vector()">;
DPPCInstrQPX.td105 def HasQPX : Predicate<"PPCSubTarget->hasQPX()">;
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelLowering.cpp68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { in PPCTargetLowering()
406 if (PPCSubTarget.isDarwin()) in PPCTargetLowering()
908 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, in SelectAddressRegImm()
957 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, in SelectAddressRegRegOnly()
1023 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, in SelectAddressRegImmShift()
1206 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { in LowerGlobalAddress()
1613 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { in LowerFormalArguments()
2443 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
2537 const PPCSubtarget &PPCSubTarget) { in PrepareCall() argument
2539 bool isPPC64 = PPCSubTarget.isPPC64(); in PrepareCall()
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DPPCISelDAGToDAG.cpp44 const PPCSubtarget &PPCSubTarget; member in __anon62a1cc8d0111::PPCDAGToDAGISel
50 PPCSubTarget(*TM.getSubtargetImpl()) {} in PPCDAGToDAGISel()
702 if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1) in SelectSETCC()
838 if (PPCSubTarget.isGigaProcessor()) in Select()
DPPCISelLowering.h237 const PPCSubtarget &PPCSubTarget; variable
DPPCInstrInfo.td353 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
354 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;