| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 726 SETULT, // 1 1 0 0 True if unordered or less than enumerator
752 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 864 SETULT, // 1 1 0 0 True if unordered or less than enumerator
890 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | Analysis.cpp | 166 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; in getFCmpCondCode()
193 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
|
| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 176 case FCmpInst::FCMP_ULT: return ISD::SETULT; in getFCmpCondCode()
188 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
208 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 228 case ISD::SETULT: in softenSetCCOperands()
1412 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1416 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
1580 case ISD::SETULT: in SimplifySetCC()
1602 case ISD::SETULT: in SimplifySetCC()
1767 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
1778 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) in SimplifySetCC()
1791 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) in SimplifySetCC()
1795 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) in SimplifySetCC()
1816 if (Cond == ISD::SETULT && in SimplifySetCC()
[all …]
|
| D | LegalizeIntegerTypes.cpp | 973 case ISD::SETULT: in PromoteSetCCOperands()
1617 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
1687 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
1796 ISD::SETULT); in ExpandIntRes_ADDSUB()
1801 ISD::SETULT); in ExpandIntRes_ADDSUB()
1810 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
2536 ISD::SETULT : ISD::SETUGT); in ExpandIntRes_UADDSUBO()
2834 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
2876 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { in IntegerExpandSetCCOperands()
2903 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
|
| D | SelectionDAGDumper.cpp | 343 case ISD::SETULT: return "setult"; in getOperationName()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelDAGToDAG.cpp | 313 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: in Select()
336 case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE: in Select()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 1968 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1972 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
2085 case ISD::SETULT: in SimplifySetCC()
2107 case ISD::SETULT: in SimplifySetCC()
2252 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); in SimplifySetCC()
2255 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) in SimplifySetCC()
2268 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) in SimplifySetCC()
2272 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) in SimplifySetCC()
2293 if (Cond == ISD::SETULT && in SimplifySetCC()
2384 isCondCodeLegal(ISD::SETULT, N0.getValueType())) in SimplifySetCC()
[all …]
|
| D | LegalizeIntegerTypes.cpp | 820 case ISD::SETULT: in PromoteSetCCOperands()
1441 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
1540 ISD::SETULT); in ExpandIntRes_ADDSUB()
1545 ISD::SETULT); in ExpandIntRes_ADDSUB()
1554 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
2235 ISD::SETULT : ISD::SETUGT); in ExpandIntRes_UADDSUBO()
2511 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
2548 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { in IntegerExpandSetCCOperands()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | README.txt | 78 SETULT unimplemented
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSelectCCInfo.td | 37 IntRegs:$fval, SETULT)),
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 48 defm LT_U : ComparisonInt<SETULT, "lt_u">;
|
| D | WebAssemblyISelLowering.cpp | 78 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 99 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in R600TargetLowering()
105 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); in R600TargetLowering()
995 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSHLParts()
996 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSHLParts()
1033 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSRXParts()
1034 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSRXParts()
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXInstrInfo.td | 549 defm SETPLTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULT, "lt">;
562 defm SETPLTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULT, "lt">;
575 defm SETPLTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULT, "lt">;
588 defm SETPLTf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETULT, SETOLT, "lt">;
597 defm SETPLTf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETULT, SETOLT, "lt">;
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrQPX.td | 1013 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETULT),
1060 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETULT),
1119 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETULT)),
1140 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETULT)),
1161 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETULT)),
|
| D | PPCISelDAGToDAG.cpp | 2112 case ISD::SETULT: return PPC::PRED_LT; in getPredicateForSetCC()
2144 case ISD::SETULT: return 0; in getCRIdxForSetCC()
2165 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
2173 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; in getVCmpInst()
2209 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break; in getVCmpInst()
3209 if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT && in combineToCMPB()
|
| D | PPCInstrInfo.td | 2950 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
3013 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3153 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3198 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3221 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3266 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3361 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
3392 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
3413 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
3434 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.td | 775 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULT),
812 (i32 GPR:$T), (i32 GPR:$F), SETULT),
844 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETULT), bb:$T),
|
| D | MBlazeInstrFPU.td | 192 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULT),
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 567 case ISD::SETULT: return PPC::PRED_LT; in getPredicateForSetCC()
603 case ISD::SETULT: return 0; in getCRIdxForSetCC()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 426 case ISD::SETULT: in NegateCC()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 963 case ISD::SETULT: in isLegalDSPCondCode()
1010 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE) in performVSELECTCombine()
1739 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1745 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1829 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 654 case ISD::SETULT: return SPCC::ICC_CS; in IntCondCCodeToICC()
678 case ISD::SETULT: return SPCC::FCC_UL; in FPCondCCodeToFCC()
|