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Searched refs:SPLAT (Results 1 – 5 of 5) sorted by relevance

/external/llvm/test/Transforms/CodeGenPrepare/X86/
Dx86-shuffle-sink.ll32 ; CHECK: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
33 ; CHECK: shl <8 x i16> %lhs, [[SPLAT]]
72 ; CHECK-SSE2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
73 ; CHECK-SSE2: ashr <4 x i32> %lhs, [[SPLAT]]
93 ; CHECK-SSE2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
94 ; CHECK-SSE2: lshr <2 x i64> %lhs, [[SPLAT]]
/external/llvm/test/Transforms/LoopVectorize/
Dinduction.ll498 ; IND: %[[SPLAT:.*]] = shufflevector <2 x i32> %[[INSERT]], <2 x i32> undef, <2 x i32> zeroinitiali…
499 ; IND: %[[START:.*]] = add <2 x i32> %[[SPLAT]], <i32 0, i32 42>
510 ; UNROLL: %[[SPLAT:.*]] = shufflevector <2 x i32> %[[INSERT]], <2 x i32> undef, <2 x i32> zeroiniti…
511 ; UNROLL: %[[START:.*]] = add <2 x i32> %[[SPLAT]], <i32 0, i32 42>
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.h179 SPLAT, enumerator
DSystemZOperators.td219 def z_splat : SDNode<"SystemZISD::SPLAT", SDT_ZVecBinaryInt>;
DSystemZISelLowering.cpp4326 return DAG.getNode(SystemZISD::SPLAT, DL, VT, Op.getOperand(0), in lowerVECTOR_SHUFFLE()
4640 OPCODE(SPLAT); in getTargetNodeName()