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Searched refs:SRC2 (Results 1 – 11 of 11) sorted by relevance

/external/bison/lib/
Dbitset.h218 #define bitset_and(DST, SRC1, SRC2) BITSET_AND_ (DST, SRC1, SRC2) argument
221 #define bitset_and_cmp(DST, SRC1, SRC2) BITSET_AND_CMP_ (DST, SRC1, SRC2) argument
224 #define bitset_andn(DST, SRC1, SRC2) BITSET_ANDN_ (DST, SRC1, SRC2) argument
227 #define bitset_andn_cmp(DST, SRC1, SRC2) BITSET_ANDN_CMP_ (DST, SRC1, SRC2) argument
230 #define bitset_or(DST, SRC1, SRC2) BITSET_OR_ (DST, SRC1, SRC2) argument
233 #define bitset_or_cmp(DST, SRC1, SRC2) BITSET_OR_CMP_ (DST, SRC1, SRC2) argument
236 #define bitset_xor(DST, SRC1, SRC2) BITSET_XOR_ (DST, SRC1, SRC2) argument
239 #define bitset_xor_cmp(DST, SRC1, SRC2) BITSET_XOR_CMP_ (DST, SRC1, SRC2) argument
244 #define bitset_and_or(DST, SRC1, SRC2, SRC3) \ argument
245 BITSET_AND_OR_ (DST, SRC1, SRC2, SRC3)
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Dbbitset.h164 #define BITSET_CHECK3_(DST, SRC1, SRC2) \ argument
166 || !BITSET_COMPATIBLE_ (DST, SRC2)) abort ();
168 #define BITSET_CHECK4_(DST, SRC1, SRC2, SRC3) \ argument
169 if (!BITSET_COMPATIBLE_ (DST, SRC1) || !BITSET_COMPATIBLE_ (DST, SRC2) \
230 #define BITSET_AND_(DST, SRC1, SRC2) (SRC1)->b.vtable->and_ (DST, SRC1, SRC2) argument
231 #define BITSET_AND_CMP_(DST, SRC1, SRC2) (SRC1)->b.vtable->and_cmp (DST, SRC1, SRC2) argument
234 #define BITSET_ANDN_(DST, SRC1, SRC2) (SRC1)->b.vtable->andn (DST, SRC1, SRC2) argument
235 #define BITSET_ANDN_CMP_(DST, SRC1, SRC2) (SRC1)->b.vtable->andn_cmp (DST, SRC1, SRC2) argument
238 #define BITSET_OR_(DST, SRC1, SRC2) (SRC1)->b.vtable->or_ (DST, SRC1, SRC2) argument
239 #define BITSET_OR_CMP_(DST, SRC1, SRC2) (SRC1)->b.vtable->or_cmp (DST, SRC1, SRC2) argument
[all …]
/external/mesa3d/src/mesa/x86/
Dx86_xform3.S43 #define SRC2 REGOFF(8, ESI) macro
125 FLD_S( SRC2 ) /* F0 F7 F6 F5 F4 */
127 FLD_S( SRC2 ) /* F1 F0 F7 F6 F5 F4 */
129 FLD_S( SRC2 ) /* F2 F1 F0 F7 F6 F5 F4 */
131 FLD_S( SRC2 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
214 FLD_S( SRC2 ) /* F0 F5 F4 */
216 FLD_S( SRC2 ) /* F1 F0 F5 F4 */
218 FLD_S( SRC2 ) /* F2 F1 F0 F5 F4 */
228 MOV_L( SRC2, EBX )
307 FLD_S( SRC2 ) /* F0 F6 F5 F4 */
[all …]
Dx86_xform4.S43 #define SRC2 REGOFF(8, ESI) macro
125 FLD_S( SRC2 ) /* F0 F7 F6 F5 F4 */
127 FLD_S( SRC2 ) /* F1 F0 F7 F6 F5 F4 */
129 FLD_S( SRC2 ) /* F2 F1 F0 F7 F6 F5 F4 */
131 FLD_S( SRC2 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
221 FLD_S( SRC2 ) /* F0 F5 F4 */
223 FLD_S( SRC2 ) /* F1 F0 F5 F4 */
225 FLD_S( SRC2 ) /* F6 F1 F0 F5 F4 */
237 MOV_L( SRC2, EBX )
317 FLD_S( SRC2 ) /* F0 F6 F5 F4 */
[all …]
Dx86_cliptest.S38 #define SRC2 REGOFF(8, ESI) macro
169 MOV_L( SRC2, EBX )
233 FLD_S( SRC2 ) /* F2 F1 F0 F3 */
335 MOV_L( SRC2, EBX )
Dx86_xform2.S43 #define SRC2 REGOFF(8, ESI) macro
/external/llvm/test/CodeGen/SystemZ/
Datomicrmw-minmax-02.ll162 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32769
163 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
164 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
179 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32766
180 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
181 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
196 ; CHECK: llilh [[SRC2:%r[0-9]+]], 1
197 ; CHECK: clrjle [[ROT:%r[0-9]+]], [[SRC2]],
198 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
213 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65534
[all …]
Datomicrmw-minmax-01.ll162 ; CHECK: llilh [[SRC2:%r[0-9]+]], 33024
163 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
164 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
179 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32256
180 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
181 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
196 ; CHECK: llilh [[SRC2:%r[0-9]+]], 256
197 ; CHECK: clrjle [[ROT:%r[0-9]+]], [[SRC2]],
198 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
213 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65024
[all …]
/external/llvm/test/CodeGen/Thumb/
Dcopy_thumb.ll10 ; CHECK-LOLOMOV-NEXT: mov [[SRC1]], [[SRC2:r[01]]]
11 ; CHECK-LOLOMOV-NEXT: mov [[SRC2]], [[TMP]]
23 ; CHECK-NOLOLOMOV: push {[[SRC2:r[01]]]}
27 ; CHECK-NOLOLOMOV-NEXT: pop {[[SRC2]]}
/external/llvm/test/CodeGen/X86/
Dmachine-cp.ll71 ; CHECK-NEXT: pcmpgtb [[SRC1]], [[SRC2:%xmm[0-9]+]]
72 ; CHECK-NEXT: pand %xmm{{[0-9]+}}, [[SRC2]]
73 ; CHECK-NEXT: movdqa [[SRC2]], [[CPY1:%xmm[0-9]+]]
/external/llvm/test/CodeGen/AMDGPU/
Dsminmax.ll118 ; GCN-DAG: v_sub_i32_e32 [[NEG2:v[0-9]+]], vcc, 0, [[SRC2:v[0-9]+]]
123 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG2]], [[SRC2]]