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Searched refs:TrySU (Results 1 – 4 of 4) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp564 SUnit *TrySU = NotReady[0]; in ListScheduleBottomUp() local
565 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU]; in ListScheduleBottomUp()
592 DEBUG(dbgs() << "Adding an edge from SU # " << TrySU->NodeNum in ListScheduleBottomUp()
594 AddPred(TrySU, SDep(Copies.front(), SDep::Order, /*Latency=*/1, in ListScheduleBottomUp()
601 << " to SU #" << TrySU->NodeNum << "\n"); in ListScheduleBottomUp()
603 AddPred(NewDef, SDep(TrySU, SDep::Order, /*Latency=*/1, in ListScheduleBottomUp()
606 TrySU->isAvailable = false; in ListScheduleBottomUp()
DScheduleDAGRRList.cpp1154 SUnit *TrySU = Interferences[i]; in PickNodeToScheduleBottomUp() local
1155 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU]; in PickNodeToScheduleBottomUp()
1168 if (!WillCreateCycle(TrySU, BtSU)) { in PickNodeToScheduleBottomUp()
1169 BacktrackBottomUp(TrySU, BtSU); in PickNodeToScheduleBottomUp()
1178 AddPred(TrySU, SDep(BtSU, SDep::Order, /*Latency=*/1, in PickNodeToScheduleBottomUp()
1185 if (!TrySU->isAvailable) { in PickNodeToScheduleBottomUp()
1189 CurSU = TrySU; in PickNodeToScheduleBottomUp()
1190 TrySU->isPending = false; in PickNodeToScheduleBottomUp()
1203 SUnit *TrySU = Interferences[0]; in PickNodeToScheduleBottomUp() local
1204 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU]; in PickNodeToScheduleBottomUp()
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/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp575 SUnit *TrySU = NotReady[0]; in ListScheduleBottomUp() local
576 SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU]; in ListScheduleBottomUp()
603 DEBUG(dbgs() << "Adding an edge from SU # " << TrySU->NodeNum in ListScheduleBottomUp()
605 AddPred(TrySU, SDep(Copies.front(), SDep::Artificial)); in ListScheduleBottomUp()
610 << " to SU #" << TrySU->NodeNum << "\n"); in ListScheduleBottomUp()
612 AddPred(NewDef, SDep(TrySU, SDep::Artificial)); in ListScheduleBottomUp()
613 TrySU->isAvailable = false; in ListScheduleBottomUp()
DScheduleDAGRRList.cpp1393 for (SUnit *TrySU : Interferences) { in PickNodeToScheduleBottomUp()
1394 SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU]; in PickNodeToScheduleBottomUp()
1406 if (!WillCreateCycle(TrySU, BtSU)) { in PickNodeToScheduleBottomUp()
1408 BacktrackBottomUp(TrySU, BtSU); in PickNodeToScheduleBottomUp()
1418 << TrySU->NodeNum << ")\n"); in PickNodeToScheduleBottomUp()
1419 AddPred(TrySU, SDep(BtSU, SDep::Artificial)); in PickNodeToScheduleBottomUp()
1423 if (!TrySU->isAvailable || !TrySU->NodeQueueId) in PickNodeToScheduleBottomUp()
1427 AvailableQueue->remove(TrySU); in PickNodeToScheduleBottomUp()
1428 CurSU = TrySU; in PickNodeToScheduleBottomUp()
1441 SUnit *TrySU = Interferences[0]; in PickNodeToScheduleBottomUp() local
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