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Searched refs:VLD (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/Target/AArch64/
DAArch64Schedule.td97 // Read the unwritten lanes of the VLD's destination registers.
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.cpp7290 SDNode *VLD = N->getOperand(0).getNode(); in CombineVLDDUP() local
7291 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) in CombineVLDDUP()
7295 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue(); in CombineVLDDUP()
7312 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue(); in CombineVLDDUP()
7313 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); in CombineVLDDUP()
7331 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) }; in CombineVLDDUP()
7332 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD); in CombineVLDDUP()
7333 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys, in CombineVLDDUP()
7338 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); in CombineVLDDUP()
7354 DCI.CombineTo(VLD, VLDDupResults); in CombineVLDDUP()
DARMInstrNEON.td192 // Classes for VLD* pseudo-instructions with multi-register operands.
541 // Classes for VLD*LN pseudo-instructions with multi-register operands.
DARMInstrInfo.td795 // Special version of addrmode6 to handle alignment encoding for VLD-dup
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td1050 // VLD/VST instructions and checking the alignment is not specified.
1061 // VLD/VST instructions and checking the alignment value.
1072 // VLD/VST instructions and checking the alignment value.
1083 // VLD/VST instructions and checking the alignment value.
1094 // for VLD/VST instructions and checking the alignment value.
1105 // encoding for VLD/VST instructions and checking the alignment value.
1115 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1136 // VLD-dup instruction and checking the alignment is not specified.
1146 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1157 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
[all …]
DARMISelLowering.cpp10120 SDNode *VLD = N->getOperand(0).getNode(); in CombineVLDDUP() local
10121 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) in CombineVLDDUP()
10125 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue(); in CombineVLDDUP()
10142 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue(); in CombineVLDDUP()
10143 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); in CombineVLDDUP()
10161 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) }; in CombineVLDDUP()
10162 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD); in CombineVLDDUP()
10163 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys, in CombineVLDDUP()
10168 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); in CombineVLDDUP()
10184 DCI.CombineTo(VLD, VLDDupResults); in CombineVLDDUP()
DARMInstrNEON.td622 // Classes for VLD* pseudo-instructions with multi-register operands.
1023 // Classes for VLD*LN pseudo-instructions with multi-register operands.
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenAsmWriter.inc6316 "ERTF128rr\000VINSERTPSrm\000VINSERTPSrr\000VLDDQUYrm\000VLDDQUrm\000VLD"
DX86GenAsmWriter1.inc7059 "ERTF128rr\000VINSERTPSrm\000VINSERTPSrr\000VLDDQUYrm\000VLDDQUrm\000VLD"