| /external/llvm/test/CodeGen/X86/ |
| D | vshift-6.ll | 13 ; VSELECT(r, B, count);
17 ; r = VSELECT(r, C, count);
19 ; VSELECT(r, r+r, count);
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| D | 2011-12-15-vec_shift.ll | 13 ; Make sure we're masking and pcmp'ing the VSELECT conditon vector.
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| D | vselect-avx.ll | 107 ; We shouldn't try to lower this directly using VSELECT because we don't have
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 163 case ISD::VSELECT: in LegalizeOp()
217 if (Node->getOpcode() == ISD::VSELECT) in LegalizeOp()
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| D | LegalizeIntegerTypes.cpp | 67 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break; in PromoteIntegerResult()
492 return DAG.getNode(ISD::VSELECT, N->getDebugLoc(), in PromoteIntRes_VSELECT()
771 case ISD::VSELECT: in PromoteIntegerOperand()
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| D | LegalizeVectorTypes.cpp | 419 case ISD::VSELECT: in SplitVectorResult()
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| D | SelectionDAG.cpp | 6006 case ISD::VSELECT: return "vselect"; in getOperationName()
6449 case ISD::VSELECT: in UnrollVectorOp()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 330 VSELECT, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 358 VSELECT, enumerator
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| D | BasicTTIImpl.h | 488 ISD = ISD::VSELECT; in getCmpSelInstrCost()
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| D | SelectionDAG.h | 832 return getNode(Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT,
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 80 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
98 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
275 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAIntType()
320 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAFloatType()
777 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); in performORCombine()
1091 case ISD::VSELECT: in PerformDAGCombine()
1593 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1606 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1611 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1614 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 292 case ISD::VSELECT: in LegalizeOp()
689 case ISD::VSELECT: in Expand()
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| D | LegalizeVectorTypes.cpp | 63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; in ScalarizeVectorResult()
452 case ISD::VSELECT: in ScalarizeVectorOperand()
590 case ISD::VSELECT: in SplitVectorResult()
1481 case ISD::VSELECT: in SplitVectorOperand()
1553 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1); in SplitVecOp_VSELECT()
1555 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1); in SplitVecOp_VSELECT()
2068 case ISD::VSELECT: in WidenVectorResult()
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| D | SelectionDAGDumper.cpp | 216 case ISD::VSELECT: return "vselect"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 75 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break; in PromoteIntegerResult()
582 return DAG.getNode(ISD::VSELECT, SDLoc(N), in PromoteIntRes_VSELECT()
896 case ISD::VSELECT: in PromoteIntegerOperand()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 726 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom); in X86TargetLowering()
785 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
808 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
902 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); in X86TargetLowering()
1107 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
1116 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); in X86TargetLowering()
1221 setOperationAction(ISD::VSELECT, MVT::v8i1, Expand); in X86TargetLowering()
1222 setOperationAction(ISD::VSELECT, MVT::v16i1, Expand); in X86TargetLowering()
1398 setOperationAction(ISD::VSELECT, VT, Legal); in X86TargetLowering()
1459 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal); in X86TargetLowering()
[all …]
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| D | X86ISelDAGToDAG.cpp | 2023 ISD::VSELECT, SDLoc(Node), Node->getValueType(0), Node->getOperand(0), in Select()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 740 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); in X86TargetLowering()
931 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); in X86TargetLowering()
932 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); in X86TargetLowering()
933 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); in X86TargetLowering()
934 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); in X86TargetLowering()
935 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); in X86TargetLowering()
1033 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); in X86TargetLowering()
1034 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); in X86TargetLowering()
1035 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); in X86TargetLowering()
1036 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); in X86TargetLowering()
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1311 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2); in LowerVSELECT()
1994 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom); in HexagonTargetLowering()
2796 case ISD::VSELECT: return LowerVSELECT(Op, DAG); in LowerOperation()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 491 setOperationAction(ISD::VSELECT, VT, Expand); in PPCTargetLowering()
592 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); in PPCTargetLowering()
593 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal); in PPCTargetLowering()
594 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); in PPCTargetLowering()
595 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); in PPCTargetLowering()
596 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); in PPCTargetLowering()
691 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); in PPCTargetLowering()
741 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); in PPCTargetLowering()
780 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal); in PPCTargetLowering()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 392 setOperationAction(ISD::VSELECT, VT, Expand); in AMDGPUTargetLowering()
428 setOperationAction(ISD::VSELECT, VT, Expand); in AMDGPUTargetLowering()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 397 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 468 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 491 setTargetDAGCombine(ISD::VSELECT); in AArch64TargetLowering()
680 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
9767 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
9884 case ISD::VSELECT: in PerformDAGCombine()
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