Searched refs:XCHG (Results 1 – 6 of 6) sorted by relevance
/external/strace/xlat/ |
D | atomic_ops.in | 3 { OR1K_ATOMIC_XCHG, "XCHG" },
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/external/llvm/lib/Target/X86/ |
D | X86SchedHaswell.td | 447 // XCHG. 454 def : InstRW<[WriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>; 461 def : InstRW<[WriteXCHGrm], (instregex "XCHG(8|16|32|64)rm")>;
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D | X86InstrInfo.td | 1846 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
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/external/llvm/lib/Transforms/Instrumentation/ |
D | AddressSanitizer.cpp | 964 } else if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) { in isInterestingMemoryAccess() local 967 *TypeSize = DL.getTypeStoreSizeInBits(XCHG->getCompareOperand()->getType()); in isInterestingMemoryAccess() 969 PtrOperand = XCHG->getPointerOperand(); in isInterestingMemoryAccess()
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/external/llvm/docs/ |
D | Atomics.rst | 435 generate an ``XCHG``, other stores generate a ``MOV``. SequentiallyConsistent 438 uses ``XCHG``, ``atomicrmw add`` and ``atomicrmw sub`` use ``XADD``, and all
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/external/llvm/test/Transforms/InstCombine/ |
D | icmp.ll | 1768 ; CHECK-NEXT: [[XCHG:%.*]] = cmpxchg i32* %sc, i32 %old_val, i32 %new_val seq_cst seq_cst
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