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Searched refs:amdinfo (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_winsys.c138 r = amdgpu_query_gpu_info(ws->dev, &ws->amdinfo); in do_winsys_init()
180 ws->info.pci_id = ws->amdinfo.asic_id; /* TODO: is this correct? */ in do_winsys_init()
181 ws->info.vce_harvest_config = ws->amdinfo.vce_harvest_config; in do_winsys_init()
278 ws->addrlib = radv_amdgpu_addr_create(&ws->amdinfo, ws->family, ws->rev_id, ws->info.chip_class); in do_winsys_init()
293 ws->info.max_shader_clock = ws->amdinfo.max_engine_clk / 1000; in do_winsys_init()
294 ws->info.max_se = ws->amdinfo.num_shader_engines; in do_winsys_init()
295 ws->info.max_sh_per_se = ws->amdinfo.num_shader_arrays_per_engine; in do_winsys_init()
299 ws->info.num_render_backends = ws->amdinfo.rb_pipes; in do_winsys_init()
300 ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq; in do_winsys_init()
301 ws->info.num_tile_pipes = radv_cik_get_num_tile_pipes(&ws->amdinfo); in do_winsys_init()
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Dradv_amdgpu_surface.c114 ADDR_HANDLE radv_amdgpu_addr_create(struct amdgpu_gpu_info *amdinfo, int family, int rev_id, in radv_amdgpu_addr_create() argument
126 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3; in radv_amdgpu_addr_create()
127 regValue.gbAddrConfig = amdinfo->gb_addr_cfg; in radv_amdgpu_addr_create()
128 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2; in radv_amdgpu_addr_create()
130 regValue.backendDisables = amdinfo->backend_disable[0]; in radv_amdgpu_addr_create()
131 regValue.pTileConfig = amdinfo->gb_tile_mode; in radv_amdgpu_addr_create()
132 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode); in radv_amdgpu_addr_create()
137 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode; in radv_amdgpu_addr_create()
138 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode); in radv_amdgpu_addr_create()
Dradv_amdgpu_surface.h31 ADDR_HANDLE radv_amdgpu_addr_create(struct amdgpu_gpu_info *amdinfo, int family, int rev_id, enum c…
Dradv_amdgpu_winsys.h41 struct amdgpu_gpu_info amdinfo; member
/external/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_winsys.c123 r = amdgpu_query_gpu_info(ws->dev, &ws->amdinfo); in do_winsys_init()
201 ws->info.pci_id = ws->amdinfo.asic_id; /* TODO: is this correct? */ in do_winsys_init()
202 ws->info.vce_harvest_config = ws->amdinfo.vce_harvest_config; in do_winsys_init()
320 !(ws->amdinfo.ids_flags & AMDGPU_IDS_FLAGS_FUSION); in do_winsys_init()
330 ws->info.max_shader_clock = ws->amdinfo.max_engine_clk / 1000; in do_winsys_init()
331 ws->info.max_se = ws->amdinfo.num_shader_engines; in do_winsys_init()
332 ws->info.max_sh_per_se = ws->amdinfo.num_shader_arrays_per_engine; in do_winsys_init()
339 ws->info.num_render_backends = ws->amdinfo.rb_pipes; in do_winsys_init()
340 ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq; in do_winsys_init()
341 ws->info.num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo); in do_winsys_init()
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Damdgpu_surface.c110 regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3; in amdgpu_addr_create()
111 regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg; in amdgpu_addr_create()
112 regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2; in amdgpu_addr_create()
114 regValue.backendDisables = ws->amdinfo.backend_disable[0]; in amdgpu_addr_create()
115 regValue.pTileConfig = ws->amdinfo.gb_tile_mode; in amdgpu_addr_create()
116 regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode); in amdgpu_addr_create()
121 regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode; in amdgpu_addr_create()
122 regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode); in amdgpu_addr_create()
Damdgpu_winsys.h72 struct amdgpu_gpu_info amdinfo; member