Searched refs:cacheline (Results 1 – 8 of 8) sorted by relevance
337 util_cpu_caps.cacheline = sizeof(void *); in util_cpu_detect()344 util_cpu_caps.cacheline = 32; in util_cpu_detect()350 unsigned int cacheline; in util_cpu_detect() local381 cacheline = ((regs2[1] >> 8) & 0xFF) * 8; in util_cpu_detect()382 if (cacheline > 0) in util_cpu_detect()383 util_cpu_caps.cacheline = cacheline; in util_cpu_detect()430 unsigned int cacheline; in util_cpu_detect() local432 cacheline = regs2[2] & 0xFF; in util_cpu_detect()433 if (cacheline > 0) in util_cpu_detect()434 util_cpu_caps.cacheline = cacheline; in util_cpu_detect()[all …]
53 unsigned cacheline; member
93 // Zero an aligned 32-byte cacheline.
86 unsigned mip_align = MAX2(64, util_cpu_caps.cacheline); in llvmpipe_texture_layout()124 lpr->row_stride[level] = align(nblocksx * block_size, util_cpu_caps.cacheline); in llvmpipe_texture_layout()
310 * In addition, this controls the spacing of cacheline-spaced size classes.319 /* Return the smallest cacheline multiple that is >= s. */
351 Make sure the instruction which starts a loop does not cross a cacheline355 In the new trace, the hot loop has an instruction which crosses a cacheline358 to grab the bytes from the next cacheline.
435 Make sure the instruction which starts a loop does not cross a cacheline439 In the new trace, the hot loop has an instruction which crosses a cacheline442 to grab the bytes from the next cacheline.
728 "arenas.cacheline", "arenas.subpage", "arenas.[tqcs]space_{min,max}", and