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Searched refs:comp0 (Results 1 – 7 of 7) sorted by relevance

/external/libvpx/libvpx/vpx_dsp/mips/
Dsad_msa.c1140 v16u8 pred0, pred1, pred2, pred3, comp0, comp1; in avgsad_16width_msa() local
1150 AVER_UB2_UB(pred0, ref0, pred1, ref1, comp0, comp1); in avgsad_16width_msa()
1151 sad += SAD_UB2_UH(src0, src1, comp0, comp1); in avgsad_16width_msa()
1152 AVER_UB2_UB(pred2, ref2, pred3, ref3, comp0, comp1); in avgsad_16width_msa()
1153 sad += SAD_UB2_UH(src2, src3, comp0, comp1); in avgsad_16width_msa()
1161 AVER_UB2_UB(pred0, ref0, pred1, ref1, comp0, comp1); in avgsad_16width_msa()
1162 sad += SAD_UB2_UH(src0, src1, comp0, comp1); in avgsad_16width_msa()
1163 AVER_UB2_UB(pred2, ref2, pred3, ref3, comp0, comp1); in avgsad_16width_msa()
1164 sad += SAD_UB2_UH(src2, src3, comp0, comp1); in avgsad_16width_msa()
1177 v16u8 comp0, comp1; in avgsad_32width_msa() local
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/external/mesa3d/src/mesa/drivers/dri/i965/
Dgen8_draw_upload.c203 uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC; in gen8_emit_vertices() local
230 case 0: comp0 = BRW_VE1_COMPONENT_STORE_0; in gen8_emit_vertices()
273 OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) | in gen8_emit_vertices()
Dbrw_draw_upload.c999 uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC; in brw_emit_vertices() local
1031 case 0: comp0 = BRW_VE1_COMPONENT_STORE_0; in brw_emit_vertices()
1053 OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) | in brw_emit_vertices()
1058 OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) | in brw_emit_vertices()
1069 uint32_t comp0 = BRW_VE1_COMPONENT_STORE_0; in brw_emit_vertices() local
1075 comp0 = BRW_VE1_COMPONENT_STORE_SRC; in brw_emit_vertices()
1086 dw1 = (comp0 << BRW_VE1_COMPONENT_0_SHIFT) | in brw_emit_vertices()
/external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/
DStoreTile.h624 …simd16scalar comp0 = _simd16_load_ps(reinterpret_cast<const float*>(pSrc + FormatTraits<DstFormat>…
633 comp0 = _simd16_max_ps(comp0, zero);
634 comp0 = _simd16_min_ps(comp0, ones);
648 comp0 = FormatTraits<R32G32B32A32_FLOAT>::convertSrgb(0, comp0);
654 comp0 = _simd16_mul_ps(comp0, _simd16_set1_ps(FormatTraits<DstFormat>::fromFloat(0)));
660 simd16scalari src0 = _simd16_cvtps_epi32(comp0); // padded byte rrrrrrrrrrrrrrrr
803 …simd16scalar comp0 = _simd16_load_ps(reinterpret_cast<const float*>(pSrc + FormatTraits<DstFormat>…
811 comp0 = _simd16_max_ps(comp0, zero);
812 comp0 = _simd16_min_ps(comp0, ones);
823 comp0 = FormatTraits<R32G32B32A32_FLOAT>::convertSrgb(0, comp0);
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/external/mesa3d/src/gallium/drivers/swr/rasterizer/core/
Dutils.h710 __m128 comp0 = _mm256_castps256_ps128(src); in Transpose() local
713 __m128i comp0i = _mm_castps_si128(comp0); in Transpose()
Dformat_traits.h38 template<UINT comp0 = 0, uint32_t comp1 = 0, uint32_t comp2 = 0, uint32_t comp3 = 0>
44 static const uint32_t s[4] = { comp0, comp1, comp2, comp3 }; in swizzle()
/external/llvm/test/CodeGen/X86/
Dblock-placement.ll365 %comp0 = icmp eq i32* undef, null
366 br i1 %comp0, label %bail, label %loop.body1