Searched refs:constrainOperandRegClass (Results 1 – 6 of 6) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 286 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
309 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
310 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
337 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
364 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rri()
365 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rri()
532 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
605 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); in ARMMaterializeGV()
681 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
1068 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); in ARMEmitStore()
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1789 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op, in constrainOperandRegClass() function in FastISel
1821 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
1843 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1844 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
1868 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
1869 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
1870 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
1894 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
1917 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
1961 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1062 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1064 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1261 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1262 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1306 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1346 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1347 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1389 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1390 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2060 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs()); in emitStore()
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| /external/llvm/include/llvm/CodeGen/ |
| D | FastISel.h | 476 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1879 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1880 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 258 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
639 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
3768 unsigned IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI()
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