Searched refs:flat_load_dwordx2 (Results 1 – 14 of 14) sorted by relevance
/external/llvm/test/CodeGen/AMDGPU/ |
D | inline-constraints.ll | 6 ; GCN: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] 16 …%v64 = tail call <2 x i32> asm sideeffect "flat_load_dwordx2 $0, $1", "=v,v"(i32 addrspace(1)* %pt…
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D | load-global-i16.ll | 35 ; GCN-HSA: flat_load_dwordx2 v 48 ; GCN-HSA: flat_load_dwordx2 168 ; GCN-HSA: flat_load_dwordx2 179 ; GCN-HSA: flat_load_dwordx2 191 ; GCN-HSA: flat_load_dwordx2 207 ; GCN-HSA: flat_load_dwordx2
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D | load-global-f32.ll | 22 ; GCN-HSA: flat_load_dwordx2
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D | load-global-f64.ll | 9 ; GCN-HSA: flat_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]
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D | load-global-i32.ll | 21 ; GCN-HSA: flat_load_dwordx2 157 ; GCN-HSA: flat_load_dwordx2 168 ; GCN-HSA: flat_load_dwordx2
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D | load-global-i64.ll | 12 ; GCN-HSA: flat_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]
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D | flat-address-space.ll | 73 ; CHECK: flat_load_dwordx2
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D | flat_atomics_i64.ll | 805 ; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} 816 ; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc 826 ; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}} 838 ; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
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D | global_atomics_i64.ll | 953 ; VI: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} 965 ; VI: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc 976 ; VI: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}} 989 ; VI: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
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D | salu-to-valu.ll | 135 ; GCN-HSA: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
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D | load-global-i8.ll | 58 ; GCN-HSA: flat_load_dwordx2
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/external/llvm/test/MC/AMDGPU/ |
D | flat.s | 159 flat_load_dwordx2 v[1:2], v[3:4] label
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/external/llvm/lib/Target/AMDGPU/ |
D | CIInstructions.td | 129 flat<0xd, 0x15>, "flat_load_dwordx2", VReg_64
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/external/llvm/test/MC/Disassembler/AMDGPU/ |
D | flat_vi.txt | 60 # VI: flat_load_dwordx2 v[1:2], v[3:4] ; encoding: [0x00,0x00,0x54,0xdc,0x03,0x00,0x00,0x01]
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