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Searched refs:flat_store_dword (Results 1 – 17 of 17) sorted by relevance

/external/llvm/test/MC/AMDGPU/
Dflat.s58 flat_store_dword v[3:4], v1 label
62 flat_store_dword v[3:4], v1 glc label
66 flat_store_dword v[3:4], v1 glc slc label
70 flat_store_dword v[3:4], v1 glc tfe label
74 flat_store_dword v[3:4], v1 glc slc tfe label
78 flat_store_dword v[3:4], v1 slc label
82 flat_store_dword v[3:4], v1 slc tfe label
86 flat_store_dword v[3:4], v1 tfe label
182 flat_store_dword v[3:4], v1 label
/external/llvm/test/CodeGen/AMDGPU/
Dflat_atomics.ll15 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
36 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
56 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
75 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
95 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
116 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
136 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
155 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
175 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
196 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
[all …]
Daddrspacecast.ll19 ; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]]
42 ; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]]
57 ; HSA: flat_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]]
117 ; HSA: flat_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]]
140 ; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
161 ; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
183 ; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
204 ; HSA: flat_store_dword {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}
232 ; HSA: flat_store_dword
Dwaitcnt-flat.ll4 ; If flat_store_dword and flat_load_dword use different registers for the data
9 ; XGCN: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[DATA:v[0-9]+]]
Dci-use-flat-for-global.ll17 ; HSA-DEFAULT: flat_store_dword
21 ; NOHSA-NODEFAULT: flat_store_dword
Dload-weird-sizes.ll23 ; CI-HSA: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VAL]]
Dhsa-func.ll52 ; HSA: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
Dhsa.ll51 ; HSA: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
Dsalu-to-valu.ll67 ; GCN-HSA: flat_store_dword {{.*}}, [[V_OUT]]
115 ; GCN-HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}
251 ; GCN-HSA: flat_store_dword {{.*}}, [[ADD]]
443 ; GCN-HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[ONE]]
Dwqm.ll286 ;VI: flat_store_dword
291 ;VI: flat_store_dword
325 ; VI: flat_store_dword
Dtarget-cpu.ll64 ; CHECK: flat_store_dword
Dflat-address-space.ll20 ; CHECK: flat_store_dword v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}, v[[DATA]]
Dload-constant-i16.ll80 ; GCN-HSA: flat_store_dword
95 ; GCN-HSA: flat_store_dword
Dload-global-i16.ll91 ; GCN-HSA: flat_store_dword
106 ; GCN-HSA: flat_store_dword
Dglobal_atomics.ll1008 ; VI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}}
1018 ; VI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}}
1027 ; VI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}}
1038 ; VI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}}
/external/llvm/docs/
DAMDGPUUsage.rst202 flat_store_dword v[1:2], v0
/external/llvm/lib/Target/AMDGPU/
DCIInstructions.td144 flat<0x1c>, "flat_store_dword", VGPR_32