| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrArithmetic.td | 314 [(set GR8:$dst, (ineg GR8:$src1)),
318 [(set GR16:$dst, (ineg GR16:$src1)),
322 [(set GR32:$dst, (ineg GR32:$src1)),
325 [(set GR64:$dst, (ineg GR64:$src1)),
331 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
335 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
339 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
342 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrArithmetic.td | 379 [(set GR8:$dst, (ineg GR8:$src1)),
383 [(set GR16:$dst, (ineg GR16:$src1)),
387 [(set GR32:$dst, (ineg GR32:$src1)),
390 [(set GR64:$dst, (ineg GR64:$src1)),
398 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
402 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
406 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
409 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
|
| D | X86InstrCompiler.td | 960 (ineg (atomic_load_8 addr:$dst)),
961 (ineg (atomic_load_16 addr:$dst)),
962 (ineg (atomic_load_32 addr:$dst)),
963 (ineg (atomic_load_64 addr:$dst))>;
|
| /external/llvm/lib/Target/PowerPC/ |
| D | README_P9.txt | 93 . Map to llvm ineg
94 (set v4i32:$rT, (ineg v4i32:$rA)) // vnegw
95 (set v2i64:$rT, (ineg v2i64:$rA)) // vnegd
|
| D | PPCInstr64Bit.td | 527 [(set i64:$rT, (ineg i64:$rA))]>;
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinInstrInfo.td | 432 (ineg off)))]>;
710 [(set D:$dst, (sra D:$src, (ineg D16L:$amount)))]>;
723 [(set D16:$dst, (srl D16:$src, (ineg D16L:$amount)))]>;
772 [(set D:$dst, (ineg D:$src))]>;
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZOperators.td | 546 def z_inegabs : PatFrag<(ops node:$src), (ineg (z_iabs node:$src))>;
555 def z_inegabs32 : PatFrag<(ops node:$src), (ineg (z_iabs32 node:$src))>;
556 def z_inegabs64 : PatFrag<(ops node:$src), (ineg (z_iabs64 node:$src))>;
|
| D | SystemZInstrInfo.td | 811 def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>;
812 def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
817 defm : SXU<ineg, LCGFR>;
|
| /external/swiftshader/src/Shader/ |
| D | ShaderCore.hpp | 223 void ineg(Vector4f &dst, const Vector4f &src);
|
| D | VertexProgram.cpp | 246 case Shader::OPCODE_INEG: ineg(d, s0); break; in program()
|
| D | PixelProgram.cpp | 160 case Shader::OPCODE_INEG: ineg(d, s0); break; in applyShader()
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 529 [(set GR32:$dst, (ineg GR32:$src)),
533 [(set GR64:$dst, (ineg GR64:$src)),
537 [(set GR64:$dst, (ineg (sext GR32:$src))),
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 939 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
945 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
1132 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 994 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
1000 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
1190 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
|
| D | ARMInstrThumb2.td | 3087 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>,
3100 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3115 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 726 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
728 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
730 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
732 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
747 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
749 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
760 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))),
762 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))),
764 def : Pat<(i64 (ineg (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)))),
1117 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 360 [(set G8RC:$rT, (ineg G8RC:$rA))]>;
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.td | 691 [(set Int16Regs:$dst, (ineg Int16Regs:$src))]>;
695 [(set Int32Regs:$dst, (ineg Int32Regs:$src))]>;
699 [(set Int64Regs:$dst, (ineg Int64Regs:$src))]>;
|
| D | NVPTXVector.td | 520 defm VNeg : IntUnaryVOp<"neg.s", ineg, INEG64, INEG32, INEG16, INEG8>;
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 592 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 698 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
|
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 764 [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 745 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
|
| /external/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.td | 693 [(set i8:$rd, (ineg i8:$src)), (implicit SREG)]>;
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrInfo.td | 1305 def: ArithLogicU_pat<ineg, NegRxRy16>;
|