Searched refs:isRegSequence (Results 1 – 22 of 22) sorted by relevance
68 !MI->isRegSequence() && in canTurnIntoImplicitDef()
198 (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()1083 assert(MI.isRegSequence() && "Invalid instruction"); in RegSequenceRewriter()1716 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && in getNextSourceFromRegSequence()1902 if (Def->isRegSequence() || Def->isRegSequenceLike()) in getNextSourceImpl()
1126 assert((MI.isRegSequence() || in getRegSequenceInputs()1129 if (!MI.isRegSequence()) in getRegSequenceInputs()
1645 if (mi->isRegSequence()) in runOnMachineFunction()
1812 } else if (TRI && (isInsertSubreg() || isRegSequence()) && MO.isImm()) { in print()
295 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), in optimizeSDPattern()341 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass)) in hasPartialWrite()405 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
3691 ResolvedDefMI->isRegSequence() || ResolvedDefMI->isImplicitDef()) { in getOperandLatency()3986 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() || in getPredicationCost()4006 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() || in getInstrLatency()
1108 let isRegSequence = 1;
180 assert(MI.isRegSequence()); in foldVGPRCopyIntoRegSequence()
255 bool isRegSequence : 1; variable
506 if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)"; in emitRecord()
323 isRegSequence = R->getValueAsBit("isRegSequence"); in CodeGenInstruction()
281 bool isRegSequence() const {
382 return MI->isInsertSubreg() || MI->isSubregToReg() || MI->isRegSequence(); in AvoidsSinking()
1079 if (mi->isRegSequence()) in runOnMachineFunction()1422 if (UseMI != RegSeq && UseMI->isRegSequence()) in HasOtherRegSequenceUses()
1459 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) { in print()
811 bool isRegSequence() const {
271 return !MI.isInsertSubreg() && !MI.isSubregToReg() && !MI.isRegSequence(); in shouldSink()
388 bit isRegSequence = 0; // Is this instruction a kind of reg sequence?
2343 DefMI->isRegSequence() || DefMI->isImplicitDef()) in getOperandLatency()2673 MI->isRegSequence() || MI->isImplicitDef()) in getInstrLatency()
912 bool Skip = MI->isCopy() || MI->isRegSequence(); in collectInBlock()
1580 let isRegSequence = 1, Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in