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/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTarget.td16 include "llvm/Intrinsics.td"
80 // is invalid for this mode/flavour.
242 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
252 // is invalid for this mode/flavour.
259 // from dwarf register number to llvm register.
267 include "llvm/Target/TargetSchedule.td"
331 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
440 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
790 // verbose-asm mode). These two values indicate the width of the first column
792 // verbose asm mode is enabled, operands will be indented to respect this.
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/external/llvm/docs/
DCodeGenerator.rst40 These interfaces are defined in ``include/llvm/Target/``.
45 ``include/llvm/CodeGen/``. At this level, concepts like "constant pool
194 The LLVM target description classes (located in the ``include/llvm/Target``
330 ``include/llvm/CodeGen``). This representation is completely target agnostic,
369 .. code-block:: llvm
382 the ``include/llvm/CodeGen/MachineInstrBuilder.h`` file. The ``BuildMI``
429 .. code-block:: llvm
439 .. code-block:: llvm
456 .. code-block:: llvm
515 a ``MachineRegisterInfo``. See ``include/llvm/CodeGen/MachineFunction.h`` for
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/external/llvm/lib/Target/X86/
DREADME.txt50 2. Code duplication (addressing mode) during isel.
215 We probably need some kind of target DAG combine hook to fix this.
368 In c99 mode, the preprocessor doesn't like assembly comments like #TRUNCATE.
750 llvm:
878 In SSE mode, we turn abs and neg into a load from the constant pool plus a xor
1242 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
1249 call void @llvm.trap()
1252 declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32)
1253 declare void @llvm.trap()
1300 call void @llvm.memcpy.i64(i8* %s, i8* %s2, i64 64, i32 16)
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/external/llvm/include/llvm/Target/
DTarget.td16 include "llvm/IR/Intrinsics.td"
110 // is invalid for this mode/flavour.
291 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
301 // is invalid for this mode/flavour.
308 // from dwarf register number to llvm register.
316 include "llvm/Target/TargetSchedule.td"
381 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
554 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
966 include "llvm/Target/GenericOpcodes.td"
1296 include "llvm/Target/TargetCallingConv.td"
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/external/swiftshader/third_party/LLVM/lib/Target/X86/
DREADME.txt61 2. Code duplication (addressing mode) during isel.
263 We probably need some kind of target DAG combine hook to fix this.
310 llvm produces:
452 In c99 mode, the preprocessor doesn't like assembly comments like #TRUNCATE.
913 llvm:
1041 In SSE mode, we turn abs and neg into a load from the constant pool plus a xor
1419 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
1426 call void @llvm.trap()
1429 declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32)
1430 declare void @llvm.trap()
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/external/python/cpython2/Misc/
DNEWS97 - Issue #28449: tarfile.open() with mode "r" or "r:" now tries to open a tar
207 that the script is in CGI mode.
222 mode no longer break tracing, trace_vinfo() now always returns a list of
316 - Issue #27983: Cause lack of llvm-profdata tool when using clang as
319 ability to find the llvm-profdata tool on MacOS and some Linuxes.
552 mode when compiled with Readline 7.
1520 - Issue #22604: Fix assertion error in debug mode when dividing a complex
1618 - Issue #8473: doctest.testfile now uses universal newline mode to read
1696 - Issue #22236: Fixed Tkinter images copying operations in NoDefaultRoot mode.
2117 ANSI mode. Initial patches by Dmitry Jemerov & Vladimir Iofik.
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