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Searched refs:qir_get_nsrc (Results 1 – 17 of 17) sorted by relevance

/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_opt_vpm.c49 for (int i = 0; i < qir_get_nsrc(inst); i++) { in qir_opt_vpm()
72 for (int j = 0; j < qir_get_nsrc(inst); j++) { in qir_opt_vpm()
97 for (int k = 0; k < qir_get_nsrc(inst); k++) { in qir_opt_vpm()
Dvc4_opt_dead_code.c57 for (int i = 0; i < qir_get_nsrc(inst); i++) { in has_nonremovable_reads()
91 for (int i = 0; i < qir_get_nsrc(inst); i++) { in qir_opt_dead_code()
132 for (int i = 0; i < qir_get_nsrc(inst); i++) { in qir_opt_dead_code()
Dvc4_qir_lower_uniforms.c92 for (int i = 0; i < qir_get_nsrc(inst); i++) { in qir_get_instruction_uniform_count()
122 uint32_t nsrc = qir_get_nsrc(inst); in qir_lower_uniforms()
158 uint32_t nsrc = qir_get_nsrc(inst); in qir_lower_uniforms()
Dvc4_opt_small_immediates.c48 for (int i = 0; i < qir_get_nsrc(inst); i++) { in qir_opt_small_immediates()
66 for (int i = 0; i < qir_get_nsrc(inst); i++) { in qir_opt_small_immediates()
Dvc4_opt_peephole_sf.c65 for (int i = 0; i < qir_get_nsrc(inst); i++) { in inst_srcs_updated()
98 for (int i = 0; i < qir_get_nsrc(a); i++) { in inst_result_equals()
Dvc4_qir_schedule.c190 for (int i = 0; i < qir_get_nsrc(inst); i++) { in calculate_deps()
308 for (int i = 0; i < qir_get_nsrc(inst); i++) { in calculate_forward_deps()
436 for (int i = 0; i < qir_get_nsrc(inst); i++) { in get_register_pressure_cost()
577 for (int i = 0; i < qir_get_nsrc(after->inst); i++) { in latency_between()
677 for (int i = 0; i < qir_get_nsrc(inst); i++) { in schedule_instructions()
Dvc4_opt_copy_propagation.c70 for (int i = 0; i < qir_get_nsrc(inst); i++) { in try_copy_prop()
116 for (int j = 0; j < qir_get_nsrc(inst); j++) { in try_copy_prop()
Dvc4_qir.c110 qir_get_nsrc(struct qinst *inst) in qir_get_nsrc() function
131 return qir_get_nsrc(inst) - 1; in qir_get_tex_uniform_src()
167 for (int i = 0; i < qir_get_nsrc(inst); i++) { in qir_has_side_effect_reads()
186 for (int i = 0; i < qir_get_nsrc(inst); i++) { in qir_has_uniform_read()
443 for (int i = 0; i < qir_get_nsrc(inst); i++) { in qir_dump_inst()
Dvc4_reorder_uniforms.c49 for (int i = 0; i < qir_get_nsrc(inst); i++) { in qir_reorder_uniforms()
Dvc4_opt_constant_folding.c61 int nsrc = qir_get_nsrc(inst); in constant_fold()
Dvc4_opt_coalesce_ff_writes.c46 for (int i = 0; i < qir_get_nsrc(inst); i++) { in qir_opt_coalesce_ff_writes()
Dvc4_qir_validate.c108 for (int i = 0; i < qir_get_nsrc(inst); i++) { in qir_validate()
Dvc4_qir_live_variables.c208 for (int i = 0; i < qir_get_nsrc(inst); i++) in qir_setup_def_use()
Dvc4_register_allocate.c309 for (int i = 0; i < qir_get_nsrc(inst); i++) { in vc4_register_allocate()
Dvc4_qpu_emit.c294 for (int i = 0; i < qir_get_nsrc(qinst); i++) { in vc4_generate_code_block()
Dvc4_qir.h575 int qir_get_nsrc(struct qinst *inst);
Dvc4_program.c2472 for (int i = 0; i < qir_get_nsrc(inst); i++) { in vc4_setup_compiled_fs_inputs()