/external/lzma/Asm/x86/ |
D | XzCrc64Opt.asm | 10 rD equ r9 define 16 SRCDAT equ rN + rD 23 movzx x6, BYTE PTR [rD] 24 inc rD 38 mov rD, r2 42 test rD, 3 49 add rN, rD 53 sub rD, rN 63 mov rD, rN 65 sub rN, rD [all …]
|
D | 7zCrcOpt.asm | 8 rD equ r2 define 21 SRCDAT equ rN + rD + 4 * 36 movzx x6, BYTE PTR [rD] 37 inc rD 54 test rD, 7 61 add rN, rD 65 sub rD, rN 71 mov rD, rN 73 sub rN, rD 110 add rD, 8 [all …]
|
/external/llvm/lib/Target/PowerPC/ |
D | PPCInstr64Bit.td | 240 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 241 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 245 def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 246 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT; 249 def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 250 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 420 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 421 "li $rD, $imm", IIC_IntSimple, 422 [(set i64:$rD, imm64SExt16:$imm)]>; 423 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), [all …]
|
D | PPCInstrInfo.td | 1073 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS), 1074 "UPDATE_VRSAVE $rD, $rS", []>; 1436 def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD), 1438 "mfbhrbe $rD, $imm", IIC_BrB, 1439 [(set i32:$rD, 1573 def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src), 1574 "lbarx $rD, $src", IIC_LdStLWARX, []>, 1577 def LHARX : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src), 1578 "lharx $rD, $src", IIC_LdStLWARX, []>, 1581 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src), [all …]
|
D | README_P9.txt | 23 (set i64:$rD, (int_ppc_altivec_vextublx i64:$rA, v16i8:$vB)) 24 (set i64:$rD, (int_ppc_altivec_vextuhlx i64:$rA, v8i16:$vB)) 25 (set i64:$rD, (int_ppc_altivec_vextuwlx i64:$rA, v4i32:$vB)) 28 (set i64:$rD, (int_ppc_altivec_vextubrx i64:$rA, v16i8:$vB)) 29 (set i64:$rD, (int_ppc_altivec_vextuhrx i64:$rA, v8i16:$vB)) 30 (set i64:$rD, (int_ppc_altivec_vextuwrx i64:$rA, v4i32:$vB)) 38 - Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD]: 41 (set i64:$rD, (int_ppc_altivec_vclzlsbb v16i8:$vB)) 42 (set i64:$rD, (int_ppc_altivec_vctzlsbb v16i8:$vB)) 99 (set v4i32:$rD, (int_ppc_altivec_vprtybw v4i32:$vB)) [all …]
|
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCInstr64Bit.td | 165 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), 166 "ldarx $rD, $ptr", LdStLDARX, 167 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; 271 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), 272 "li $rD, $imm", IntGeneral, 273 [(set G8RC:$rD, immSExt16:$imm)]>; 274 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), 275 "lis $rD, $imm", IntGeneral, 276 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 335 def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), [all …]
|
D | PPCInstrInfo.td | 370 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS), 371 "UPDATE_VRSAVE $rD, $rS", []>; 634 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src), 635 "lwarx $rD, $src", LdStLWARX, 636 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>; 653 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), 654 "lbz $rD, $src", LdStGeneral, 655 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; 656 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src), 657 "lha $rD, $src", LdStLHA, [all …]
|
/external/valgrind/VEX/priv/ |
D | guest_arm_toIR.c | 7890 void mk_neon_elem_load_to_one_lane( UInt rD, UInt inc, UInt index, in mk_neon_elem_load_to_one_lane() argument 7896 putDRegI64(rD, triop(Iop_SetElem8x8, getDRegI64(rD), mkU8(index), in mk_neon_elem_load_to_one_lane() 7900 putDRegI64(rD, triop(Iop_SetElem16x4, getDRegI64(rD), mkU8(index), in mk_neon_elem_load_to_one_lane() 7904 putDRegI64(rD, triop(Iop_SetElem32x2, getDRegI64(rD), mkU8(index), in mk_neon_elem_load_to_one_lane() 7913 putDRegI64(rD + i * inc, in mk_neon_elem_load_to_one_lane() 7915 getDRegI64(rD + i * inc), in mk_neon_elem_load_to_one_lane() 7923 putDRegI64(rD + i * inc, in mk_neon_elem_load_to_one_lane() 7925 getDRegI64(rD + i * inc), in mk_neon_elem_load_to_one_lane() 7933 putDRegI64(rD + i * inc, in mk_neon_elem_load_to_one_lane() 7935 getDRegI64(rD + i * inc), in mk_neon_elem_load_to_one_lane() [all …]
|
D | host_arm64_defs.c | 888 ARM64Instr* ARM64Instr_LdSt64 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { in ARM64Instr_LdSt64() argument 892 i->ARM64in.LdSt64.rD = rD; in ARM64Instr_LdSt64() 896 ARM64Instr* ARM64Instr_LdSt32 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { in ARM64Instr_LdSt32() argument 900 i->ARM64in.LdSt32.rD = rD; in ARM64Instr_LdSt32() 904 ARM64Instr* ARM64Instr_LdSt16 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { in ARM64Instr_LdSt16() argument 908 i->ARM64in.LdSt16.rD = rD; in ARM64Instr_LdSt16() 912 ARM64Instr* ARM64Instr_LdSt8 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { in ARM64Instr_LdSt8() argument 916 i->ARM64in.LdSt8.rD = rD; in ARM64Instr_LdSt8() 1063 ARM64Instr* ARM64Instr_VCvtI2F ( ARM64CvtOp how, HReg rD, HReg rS ) { in ARM64Instr_VCvtI2F() argument 1067 i->ARM64in.VCvtI2F.rD = rD; in ARM64Instr_VCvtI2F() [all …]
|
D | host_arm_defs.c | 1137 Bool isLoad, HReg rD, ARMAMode1* amode ) { in ARMInstr_LdSt32() argument 1142 i->ARMin.LdSt32.rD = rD; in ARMInstr_LdSt32() 1149 HReg rD, ARMAMode2* amode ) { in ARMInstr_LdSt16() argument 1155 i->ARMin.LdSt16.rD = rD; in ARMInstr_LdSt16() 1161 Bool isLoad, HReg rD, ARMAMode1* amode ) { in ARMInstr_LdSt8U() argument 1166 i->ARMin.LdSt8U.rD = rD; in ARMInstr_LdSt8U() 1171 ARMInstr* ARMInstr_Ld8S ( ARMCondCode cc, HReg rD, ARMAMode2* amode ) { in ARMInstr_Ld8S() argument 1175 i->ARMin.Ld8S.rD = rD; in ARMInstr_Ld8S() 1534 ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ) { in ARMInstr_Add32() argument 1541 i->ARMin.Alu.dst = rD; in ARMInstr_Add32() [all …]
|
D | host_arm64_defs.h | 584 HReg rD; member 590 HReg rD; member 596 HReg rD; member 602 HReg rD; member 738 HReg rD; // dst, a D or S register member 744 HReg rD; // dst, a W or X register member 872 HReg rD; member 952 extern ARM64Instr* ARM64Instr_VCvtI2F ( ARM64CvtOp how, HReg rD, HReg rS ); 953 extern ARM64Instr* ARM64Instr_VCvtF2I ( ARM64CvtOp how, HReg rD, HReg rS, 978 extern ARM64Instr* ARM64Instr_VDfromX ( HReg rD, HReg rX );
|
D | host_arm_defs.h | 674 HReg rD; member 682 HReg rD; member 689 HReg rD; member 695 HReg rD; member 969 HReg rD; member 1047 extern ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 );
|
/external/aac/libFDK/src/ |
D | FDK_crc.cpp | 410 CCrcRegData *rD = &hCrcInfo->crcRegData[reg]; in crcCalc() local 415 FDKpushBiDirectional(&bsReader, -(INT)(rD->validBits-FDKgetValidBits(&bsReader))); in crcCalc() 419 FDKpushBiDirectional(&bsReader, rD->validBits); in crcCalc() 423 rBits = (rD->maxBits>=0) ? rD->maxBits : -rD->maxBits; /* ramaining bits */ in crcCalc() 424 if ((rD->maxBits>0) && (((INT)rD->bitBufCntBits>>3<<3)<rBits) ) { in crcCalc() 425 bits = rD->bitBufCntBits; in crcCalc()
|
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
D | reorder-global-variables.ll | 7 ; RUN: -i %s --assemble --disassemble --dis-flags=-rD \ 11 ; RUN: -i %s --assemble --disassemble --dis-flags=-rD \ 17 ; RUN: -i %s --disassemble --dis-flags=-rD \ 21 ; RUN: -i %s --disassemble --dis-flags=-rD \ 27 ; RUN: -i %s --disassemble --dis-flags=-rD \ 32 ; RUN: -i %s --disassemble --dis-flags=-rD \ 39 ; RUN: mips32 -i %s --dis-flags=-rD --args -O2 -sz-seed=1 \
|
/external/compiler-rt/lib/builtins/arm/ |
D | sync-ops.h | 51 #define MINMAX_4(rD, rN, rM, cmp_kind) \ argument 53 mov rD, rM ; \ 55 mov##cmp_kind rD, rN
|
D | sync_fetch_and_xor_4.S | 17 #define xor_4(rD, rN, rM) eor rD, rN, rM argument
|
D | sync_fetch_and_sub_4.S | 18 #define sub_4(rD, rN, rM) sub rD, rN, rM argument
|
D | sync_fetch_and_nand_4.S | 17 #define nand_4(rD, rN, rM) bic rD, rN, rM argument
|
D | sync_fetch_and_and_4.S | 17 #define and_4(rD, rN, rM) and rD, rN, rM argument
|
D | sync_fetch_and_or_4.S | 17 #define or_4(rD, rN, rM) orr rD, rN, rM argument
|
D | sync_fetch_and_add_4.S | 18 #define add_4(rD, rN, rM) add rD, rN, rM argument
|
D | sync_fetch_and_max_4.S | 17 #define max_4(rD, rN, rM) MINMAX_4(rD, rN, rM, gt) argument
|
D | sync_fetch_and_min_4.S | 17 #define min_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lt) argument
|
D | sync_fetch_and_umax_4.S | 17 #define umax_4(rD, rN, rM) MINMAX_4(rD, rN, rM, hi) argument
|
D | sync_fetch_and_umin_4.S | 17 #define umin_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lo) argument
|