Searched refs:s_lshl_b32 (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | shl_add_constant.ll | 59 ; SI: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3
75 ; SI: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3
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| D | lshl.ll | 4 ;CHECK: s_lshl_b32 s{{[0-9]}}, s{{[0-9]}}, 1
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| D | trunc.ll | 24 ; SI: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
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| D | and.ll | 220 ; SI: s_lshl_b32 [[A]], [[A]], 1
221 ; SI: s_lshl_b32 [[B]], [[B]], 1
342 ; SI: s_lshl_b32 [[A]], [[A]], 1{{$}}
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| D | indirect-addressing-si.ll | 460 ; GCN: s_lshl_b32 [[IDX_SHL:s[0-9]+]], [[IDX_IN]]
476 ; GCN: s_lshl_b32 [[IDX_SHL:s[0-9]+]], [[IDX_IN]]
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| D | insert_vector_elt.ll | 336 ; GCN-DAG: s_lshl_b32 [[SCALEDIDX:s[0-9]+]], [[IDX]], 1{{$}}
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| /external/llvm/test/MC/AMDGPU/ |
| D | sop2.s | 107 s_lshl_b32 s2, s4, s6 label
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| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | sop2_vi.txt | 51 # VI: s_lshl_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8e]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 278 defm S_LSHL_B32 : SOP2_32 <sop2<0x1e, 0x1c>, "s_lshl_b32",
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