/external/llvm/test/CodeGen/NVPTX/ |
D | compare-int.ll | 13 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 22 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 31 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 40 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 49 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 58 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 67 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 76 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 85 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 94 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] [all …]
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D | i1-int-to-fp.ll | 5 ; CHECK: selp 14 ; CHECK: selp 23 ; CHECK: selp 32 ; CHECK: selp
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D | inline-asm.ll | 13 ; CHECK: selp.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %p{{[0-9]+}} 14 %0 = tail call i32 asm "selp.b32 $0, $1, $2, $3;", "=r,r,r,b"(i32 %a, i32 %b, i1 %cond)
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D | add-128bit.ll | 11 ; CHECK: selp.b64 12 ; CHECK: selp.b64
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D | shift-parts.ll | 13 ; CHECK: selp.b64 31 ; CHECK: selp.b64
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D | bug22246.ll | 9 ; CHECK: selp.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %p{{[0-9]+}}
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/external/swiftshader/third_party/LLVM/test/CodeGen/PTX/ |
D | setp.ll | 5 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]]; 14 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]]; 23 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]]; 32 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]]; 41 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]]; 50 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]]; 59 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]]; 68 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]]; 77 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]]; 86 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0]]; [all …]
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D | selp.ll | 4 ; CHECK: selp.u32 %ret{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %p{{[0-9]+}}; 10 ; CHECK: selp.u64 %ret{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}, %p{{[0-9]+}}; 16 ; CHECK: selp.f32 %ret{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %p{{[0-9]+}}; 22 ; CHECK: selp.f64 %ret{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %p{{[0-9]+}};
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D | cvt.ll | 9 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0:[0-9]+]]; 20 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0:[0-9]+]]; 31 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0:[0-9]+]]; 42 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0:[0-9]+]]; 53 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0:[0-9]+]]; 64 ; CHECK: selp.u16 %ret{{[0-9]+}}, 1, 0, %p{{[0-9]+}}; 101 ; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p{{[0-9]+}}; 138 ; CHECK: selp.u64 %ret{{[0-9]+}}, 1, 0, %p{{[0-9]+}}; 177 ; CHECK: selp.f32 %ret{{[0-9]+}}, %f0, %f1, %p{{[0-9]+}}; 237 ; CHECK: selp.f64 %ret{{[0-9]+}}, %fd0, %fd1, %p{{[0-9]+}};
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/external/iproute2/ip/ |
D | xfrm_policy.c | 253 char *selp = NULL; in xfrm_policy_modify() local 348 if (selp) in xfrm_policy_modify() 350 selp = *argv; in xfrm_policy_modify() 566 char *selp = NULL; in xfrm_policy_get_or_delete() local 624 if (selp) in xfrm_policy_get_or_delete() 626 selp = *argv; in xfrm_policy_get_or_delete() 645 if (!selp && !indexp) { in xfrm_policy_get_or_delete() 649 if (selp && indexp) in xfrm_policy_get_or_delete() 771 char *selp = NULL; in xfrm_policy_list_or_deleteall() local 824 if (selp) in xfrm_policy_list_or_deleteall() [all …]
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/external/llvm/lib/Target/NVPTX/ |
D | NVPTXInstrInfo.td | 1318 // Selection instructions (selp) 1323 // selp instructions that don't have any pattern matches; we explicitly use 1329 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>; 1332 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>; 1335 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>; 1338 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>; 1346 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), 1351 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), 1356 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), 1361 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), [all …]
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D | NVPTXVector.td | 897 string t1 = !strconcat("selp.", type);
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D | NVPTXIntrinsics.td | 52 !strconcat("selp.u32 \t$dst, 1, 0, %p2; \n\t", 61 !strconcat("selp.u32 \t$dst, 1, 0, %p2; \n\t",
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
D | PTXInstrInfo.td | 464 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"), 468 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"), 472 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"), 602 // .selp
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/external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
D | nv50_ir_lowering_nvc0.cpp | 1310 Instruction *selp = in handleSharedATOM() local 1313 selp->src(2).mod = Modifier(NV50_IR_MOD_NOT); in handleSharedATOM() 1314 selp->setPredicate(CC_P, ld->getDef(1)); in handleSharedATOM() 1316 stVal = selp->getDef(0); in handleSharedATOM()
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/external/llvm/docs/ |
D | NVPTXUsage.rst | 959 selp.f32 %f99, 0f00000000, %f98, %p15; 961 selp.f32 %f110, 0f7F800000, %f99, %p16;
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