| /external/libunwind/src/dwarf/ |
| D | Gparser.c | 51 set_reg (dwarf_state_record_t *sr, unw_word_t regnum, dwarf_where_t where, in set_reg() function
154 set_reg (sr, regnum, DWARF_WHERE_CFAREL, val * dci->data_align); in run_cfi_program()
163 set_reg (sr, regnum, DWARF_WHERE_CFAREL, val * dci->data_align); in run_cfi_program()
172 set_reg (sr, regnum, DWARF_WHERE_CFAREL, val * dci->data_align); in run_cfi_program()
219 set_reg (sr, regnum, DWARF_WHERE_UNDEF, 0); in run_cfi_program()
226 set_reg (sr, regnum, DWARF_WHERE_SAME, 0); in run_cfi_program()
234 set_reg (sr, regnum, DWARF_WHERE_REG, val); in run_cfi_program()
271 set_reg (sr, DWARF_CFA_REG_COLUMN, DWARF_WHERE_REG, regnum); in run_cfi_program()
272 set_reg (sr, DWARF_CFA_OFF_COLUMN, 0, val); /* NOT factored! */ in run_cfi_program()
280 set_reg (sr, DWARF_CFA_REG_COLUMN, DWARF_WHERE_REG, regnum); in run_cfi_program()
[all …]
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| /external/libunwind/src/ia64/ |
| D | Gparser.c | 155 set_reg (struct ia64_reg_info *reg, enum ia64_where where, int when, in set_reg() function
299 set_reg (sr->curr.reg + unw.save_order[i], IA64_WHERE_GR, in desc_prologue()
328 set_reg (sr->curr.reg + IA64_REG_B1 + i, IA64_WHERE_GR, in desc_br_gr()
343 set_reg (sr->curr.reg + IA64_REG_B1 + i, IA64_WHERE_SPILL_HOME, in desc_br_mem()
361 set_reg (sr->curr.reg + IA64_REG_R4 + i, IA64_WHERE_SPILL_HOME, in desc_frgr_mem()
372 set_reg (sr->curr.reg + base + i, IA64_WHERE_SPILL_HOME, in desc_frgr_mem()
389 set_reg (sr->curr.reg + IA64_REG_F2 + i, IA64_WHERE_SPILL_HOME, in desc_fr_mem()
406 set_reg (sr->curr.reg + IA64_REG_R4 + i, IA64_WHERE_GR, in desc_gr_gr()
421 set_reg (sr->curr.reg + IA64_REG_R4 + i, IA64_WHERE_SPILL_HOME, in desc_gr_mem()
432 set_reg (sr->curr.reg + IA64_REG_PSP, IA64_WHERE_NONE, in desc_mem_stack_f()
[all …]
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| /external/v8/src/arm64/ |
| D | simulator-arm64.h | 355 void set_reg(unsigned code, T value,
364 set_reg(code, value, r31mode);
369 set_reg(code, value, r31mode);
396 set_reg(kLinkRegCode, value);
402 set_reg(31, value, Reg31IsStackPointer);
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| D | simulator-arm64.cc | 940 set_reg<T>(instr->Rd(), new_val); in AddSubWithCarry()
1015 set_reg<T>(instr->Rd(), result); in Extract()
1334 set_reg(instr->Rd(), instr->ImmPCOffsetTarget()); in VisitPCRelAddressing()
1446 set_reg<T>(instr->Rd(), new_val, instr->RdMode()); in AddSubHelper()
1546 set_reg<T>(instr->Rd(), result, instr->RdMode()); in LogicalHelper()
1905 set_reg(addr_reg, address + offset, Reg31IsStackPointer); in LoadStoreWriteBack()
2099 set_reg<T>(instr->Rd(), result); in DataProcessing2Source()
2221 set_reg<T>(instr->Rd(), result); in BitfieldHelper()
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| /external/libunwind/scripts/ |
| D | kernel-files.txt | 17 $udir/src/mi/Gset_reg.c $kdir/unwind/set_reg.c
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_uvd.c | 103 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val) in set_reg() function
123 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, addr); in send_cmd()
124 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, addr >> 32); in send_cmd()
127 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off); in send_cmd()
128 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4); in send_cmd()
130 set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd << 1); in send_cmd()
1149 set_reg(dec, RUVD_ENGINE_CNTL, 1); in ruvd_end_frame()
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| /external/libunwind/include/ |
| D | libunwind-common.h | 253 #define unw_set_reg UNW_OBJ(set_reg)
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| D | libunwind-common.h.in | 220 #define unw_set_reg UNW_OBJ(set_reg)
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| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 970 void set_reg(unsigned code,
1034 void set_reg(unsigned size,
|