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Searched refs:subu (Results 1 – 25 of 126) sorted by relevance

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/external/llvm/test/CodeGen/Mips/llvm-ir/
Dsub.ll38 ; NOT-MM: subu $[[T0:[0-9]+]], $4, $5
54 ; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5
58 ; R2-R6: subu $[[T0:[0-9]+]], $4, $5
72 ; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5
76 ; R2-R6: subu $[[T0:[0-9]+]], $4, $5
90 ; NOT-MM: subu $2, $4, $5
102 ; GP32: subu $3, $5, $7
105 ; GP32: subu $2, $4, $[[T1]]
123 ; GP32-NOT-MM: subu $[[T6:[0-9]+]], $7, $[[T5]]
124 ; GP32-NOT-MM: subu $2, $4, $[[T3]]
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/m88k/
Dobsd.S58 subu %r31, %r31, 32
99 subu %r31, %r30, 32
167 subu %r31, %r30, 16
181 subu %r31, %r31, 16
187 subu %r31, %r31, (8 * 4)
204 subu %r31, %r30, 16
/external/libjpeg-turbo/simd/
Djsimd_mips_dspr2.S319 subu.ph t2, t2, t8
322 subu t0, 128
405 subu t8, t9, t7
913 subu t1, t0, t7 // t1 = thiscolsum * 3
980 subu t1, t0, t6 // t1 = thiscolsum * 3
993 subu t0, a0, t0
1136 subu s2, t7, s2
1237 subu s2, t7, s2
1340 subu v0, v0, s0
1365 subu t6, v1, v0 // t6 = 16384 - tmp_smoot_f * 80
[all …]
/external/llvm/test/MC/Mips/
Dmips-alu-instructions.s90 # CHECK: subu $4, $3, $5 # encoding: [0x23,0x20,0x65,0x00]
115 subu $4,$3,$5
116 subu $sp,$sp,40
134 # CHECK: subu $9, $9, $3 # encoding: [0x23,0x48,0x23,0x01]
146 subu $9, $3
148 subu $9, 10
Drotations64.s10 # CHECK-64: subu $1, $zero, $5 # encoding: [0x00,0x05,0x08,0x23]
14 # CHECK-64R: subu $1, $zero, $5 # encoding: [0x00,0x05,0x08,0x23]
17 # CHECK-64: subu $1, $zero, $6 # encoding: [0x00,0x06,0x08,0x23]
51 # CHECK-64: subu $1, $zero, $5 # encoding: [0x00,0x05,0x08,0x23]
57 # CHECK-64: subu $1, $zero, $6 # encoding: [0x00,0x06,0x08,0x23]
Dmicromips-alu-instructions.s17 # CHECK-EL: subu $4, $3, $5 # encoding: [0xa3,0x00,0xd0,0x21]
60 # CHECK-EB: subu $4, $3, $5 # encoding: [0x00,0xa3,0x21,0xd0]
100 subu $4, $3, $5
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dvector-arith.ll188 ; MIPS32: subu
189 ; MIPS32: subu
190 ; MIPS32: subu
191 ; MIPS32: subu
192 ; MIPS32: subu
193 ; MIPS32: subu
194 ; MIPS32: subu
195 ; MIPS32: subu
196 ; MIPS32: subu
197 ; MIPS32: subu
[all …]
Dvector-align.ll96 ; MIPS32: subu
97 ; MIPS32: subu
98 ; MIPS32: subu
99 ; MIPS32: subu
/external/llvm/test/CodeGen/Mips/
Dcttz-v.ll13 ; MIPS32-DAG: subu $2, $[[R4]], $[[R3]]
19 ; MIPS32-DAG: subu $3, $[[R4]], $[[R8]]
27 ; MIPS64-DAG: subu $2, $[[R4]], $[[R3]]
34 ; MIPS64-DAG: subu $3, $[[R4]], $[[R8]]
D2008-06-05-Carry.ll16 ; CHECK: subu
19 ; CHECK: subu
D2008-08-06-Alloca.ll5 ; CHECK: subu ${{[0-9]+}}, $sp
6 ; CHECK: subu ${{[0-9]+}}, $sp
Dllcarry.ll29 ; 16: subu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
33 ; 16: subu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
Dmadd-msub.ll156 ; 32R6-DAG: subu $2, $[[T5]], $[[T4]]
157 ; 32R6-DAG: subu $3, $6, $[[T1]]
187 ; 32-DAG: [[m:m]]subu ${{[45]}}, ${{[45]}}
203 ; 32R6-DAG: subu $3, $6, $[[T1]]
241 ; 32R6-DAG: subu $2, $6, $[[T3]]
242 ; 32R6-DAG: subu $3, $7, $[[T1]]
Dalloca.ll5 ; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
7 ; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]]
31 ; CHECK: subu $[[T0:[0-9]+]], $sp
Dlargeimm1.ll13 ; CHECK: subu $sp, $sp, $[[R1]]
/external/llvm/test/CodeGen/Mips/cstmaterialization/
Dstack.ll8 ; (d)subu and (d)addu rather than just (d)addu. The (d)subu sequences are
21 ; CHECK-MIPS32: subu $sp, $sp, $[[R0]]
46 ; CHECK-MIPSN32: subu $sp, $sp, $[[R0]]
/external/valgrind/none/tests/mips32/
DMIPS32int.stdout.exp-mips32-LE961 subu $t0, $t1, $t2 :: rd 0x31415926 rs 0x31415927, rt 0x00000001
962 subu $t0, $t1, $t2 :: rd 0x31414817 rs 0x31415927, rt 0x00001110
963 subu $t0, $t1, $t2 :: rd 0xffffff01 rs 0x00000000, rt 0x000000ff
964 subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
965 subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000001
966 subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
967 subu $t0, $t1, $t2 :: rd 0x80000001 rs 0x80000000, rt 0xffffffff
968 subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
969 subu $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
970 subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
[all …]
DMIPS32int.stdout.exp-mips32-BE961 subu $t0, $t1, $t2 :: rd 0x31415926 rs 0x31415927, rt 0x00000001
962 subu $t0, $t1, $t2 :: rd 0x31414817 rs 0x31415927, rt 0x00001110
963 subu $t0, $t1, $t2 :: rd 0xffffff01 rs 0x00000000, rt 0x000000ff
964 subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
965 subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000001
966 subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
967 subu $t0, $t1, $t2 :: rd 0x80000001 rs 0x80000000, rt 0xffffffff
968 subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
969 subu $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
970 subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
[all …]
DMIPS32int.stdout.exp-mips32r2-BE1439 subu $t0, $t1, $t2 :: rd 0x31415926 rs 0x31415927, rt 0x00000001
1440 subu $t0, $t1, $t2 :: rd 0x31414817 rs 0x31415927, rt 0x00001110
1441 subu $t0, $t1, $t2 :: rd 0xffffff01 rs 0x00000000, rt 0x000000ff
1442 subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
1443 subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000001
1444 subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1445 subu $t0, $t1, $t2 :: rd 0x80000001 rs 0x80000000, rt 0xffffffff
1446 subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
1447 subu $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
1448 subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
[all …]
DMIPS32int.stdout.exp-mips32r2-LE1439 subu $t0, $t1, $t2 :: rd 0x31415926 rs 0x31415927, rt 0x00000001
1440 subu $t0, $t1, $t2 :: rd 0x31414817 rs 0x31415927, rt 0x00001110
1441 subu $t0, $t1, $t2 :: rd 0xffffff01 rs 0x00000000, rt 0x000000ff
1442 subu $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
1443 subu $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0x00000001
1444 subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1445 subu $t0, $t1, $t2 :: rd 0x80000001 rs 0x80000000, rt 0xffffffff
1446 subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
1447 subu $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
1448 subu $t0, $t1, $t2 :: rd 0x00000000 rs 0x80000000, rt 0x80000000
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
D2008-08-06-Alloca.ll1 ; RUN: llc < %s -march=mips | grep {subu.*sp} | count 2
2 ; RUN: llc < %s -march=mips -regalloc=basic | grep {subu.*sp} | count 2
Dalloca.ll5 ; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
8 ; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]]
39 ; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
D2008-06-05-Carry.ll2 ; RUN: grep subu %t | count 2
/external/valgrind/coregrind/m_syswrap/
Dsyscall-mips32-linux.S81 subu $29, $29, 56 #set up the steck frame,
120 subu $29, $29, 24 #set up the steck frame,
/external/llvm/test/MC/Mips/micromips-dspr2/
Dvalid.s100 subu.ph $3, $4, $5 # CHECK: subu.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x0d]
102 subu.qb $3, $4, $5 # CHECK: subu.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xcd]

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