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Searched refs:surf_level (Results 1 – 2 of 2) sorted by relevance

/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_surface.c169 struct radeon_surf_level *surf_level; in radv_compute_level() local
202 surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level]; in radv_compute_level()
203 surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign); in radv_compute_level()
204 surf_level->slice_size = AddrSurfInfoOut->sliceSize; in radv_compute_level()
205 surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe); in radv_compute_level()
206 surf_level->npix_x = u_minify(surf->npix_x, level); in radv_compute_level()
207 surf_level->npix_y = u_minify(surf->npix_y, level); in radv_compute_level()
208 surf_level->npix_z = u_minify(surf->npix_z, level); in radv_compute_level()
209 surf_level->nblk_x = AddrSurfInfoOut->pitch; in radv_compute_level()
210 surf_level->nblk_y = AddrSurfInfoOut->height; in radv_compute_level()
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/external/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_surface.c157 struct radeon_surf_level *surf_level; in compute_level() local
191 surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level]; in compute_level()
192 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign); in compute_level()
193 surf_level->slice_size = AddrSurfInfoOut->sliceSize; in compute_level()
194 surf_level->nblk_x = AddrSurfInfoOut->pitch; in compute_level()
195 surf_level->nblk_y = AddrSurfInfoOut->height; in compute_level()
199 surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED; in compute_level()
202 surf_level->mode = RADEON_SURF_MODE_1D; in compute_level()
205 surf_level->mode = RADEON_SURF_MODE_2D; in compute_level()
216 surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize; in compute_level()
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