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Searched refs:swtcl (Results 1 – 11 of 11) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_swtcl.c67 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
68 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
69 rmesa->radeon.swtcl.vertex_attr_count++; \
75 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
76 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
77 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \
78 rmesa->radeon.swtcl.vertex_attr_count++; \
107 rmesa->radeon.swtcl.vertex_attr_count = 0; in radeonSetVertexFormat()
112 if ( !rmesa->swtcl.needproj || in radeonSetVertexFormat()
125 rmesa->swtcl.coloroffset = offset; in radeonSetVertexFormat()
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Dradeon_dma.c430 radeon_bo_unmap(rmesa->swtcl.bo); in rcommon_flush_last_swtcl_prim()
436 rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == in rcommon_flush_last_swtcl_prim()
444 rmesa->swtcl.numverts = 0; in rcommon_flush_last_swtcl_prim()
446 radeon_bo_unref(rmesa->swtcl.bo); in rcommon_flush_last_swtcl_prim()
447 rmesa->swtcl.bo = NULL; in rcommon_flush_last_swtcl_prim()
476 assert( vsize == rmesa->swtcl.vertex_size * 4 ); in rcommonAllocDmaLowVerts()
479 rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == in rcommonAllocDmaLowVerts()
482 if (!rmesa->swtcl.bo) { in rcommonAllocDmaLowVerts()
483 rmesa->swtcl.bo = first_elem(&rmesa->dma.reserved)->bo; in rcommonAllocDmaLowVerts()
484 radeon_bo_ref(rmesa->swtcl.bo); in rcommonAllocDmaLowVerts()
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Dradeon_tcl.c459 rmesa->swtcl.vertex_format = 0; in transition_to_swtnl()
506 rmesa->swtcl.vertex_format = 0; in transition_to_hwtnl()
Dradeon_context.h425 struct r100_swtcl_info swtcl; member
Dradeon_common_context.h409 struct radeon_swtcl_info swtcl; member
Dradeon_context.c212 rmesa->radeon.swtcl.RenderIndex = ~0; in r100CreateContext()
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_swtcl.c62 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
63 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
64 rmesa->radeon.swtcl.vertex_attr_count++; \
70 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
71 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
72 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \
73 rmesa->radeon.swtcl.vertex_attr_count++; \
96 rmesa->radeon.swtcl.vertex_attr_count = 0; in r200SetVertexFormat()
101 if ( !rmesa->swtcl.needproj || in r200SetVertexFormat()
117 rmesa->swtcl.coloroffset = offset; in r200SetVertexFormat()
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Dradeon_dma.c430 radeon_bo_unmap(rmesa->swtcl.bo); in rcommon_flush_last_swtcl_prim()
436 rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == in rcommon_flush_last_swtcl_prim()
444 rmesa->swtcl.numverts = 0; in rcommon_flush_last_swtcl_prim()
446 radeon_bo_unref(rmesa->swtcl.bo); in rcommon_flush_last_swtcl_prim()
447 rmesa->swtcl.bo = NULL; in rcommon_flush_last_swtcl_prim()
476 assert( vsize == rmesa->swtcl.vertex_size * 4 ); in rcommonAllocDmaLowVerts()
479 rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 == in rcommonAllocDmaLowVerts()
482 if (!rmesa->swtcl.bo) { in rcommonAllocDmaLowVerts()
483 rmesa->swtcl.bo = first_elem(&rmesa->dma.reserved)->bo; in rcommonAllocDmaLowVerts()
484 radeon_bo_ref(rmesa->swtcl.bo); in rcommonAllocDmaLowVerts()
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Dradeon_common_context.h409 struct radeon_swtcl_info swtcl; member
Dr200_context.h613 struct r200_swtcl_info swtcl; member
Dr200_context.c249 rmesa->radeon.swtcl.RenderIndex = ~0; in r200CreateContext()